Lines Matching +full:4 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2023, Intel Corporation. */
4 /* Machine-generated file */
9 #define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4))
10 #define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4))
19 #define PF_FW_ARQLEN_ARQVFE_M BIT(28)
20 #define PF_FW_ARQLEN_ARQOVFL_M BIT(29)
21 #define PF_FW_ARQLEN_ARQCRIT_M BIT(30)
22 #define PF_FW_ARQLEN_ARQENABLE_M BIT(31)
30 #define PF_FW_ATQLEN_ATQVFE_M BIT(28)
31 #define PF_FW_ATQLEN_ATQOVFL_M BIT(29)
32 #define PF_FW_ATQLEN_ATQCRIT_M BIT(30)
33 #define VF_MBX_ARQLEN(_VF) (0x0022BC00 + ((_VF) * 4))
34 #define VF_MBX_ATQLEN(_VF) (0x0022A800 + ((_VF) * 4))
35 #define PF_FW_ATQLEN_ATQENABLE_M BIT(31)
43 #define PF_MBX_ARQLEN_ARQCRIT_M BIT(30)
44 #define PF_MBX_ARQLEN_ARQENABLE_M BIT(31)
52 #define PF_MBX_ATQLEN_ATQCRIT_M BIT(30)
53 #define PF_MBX_ATQLEN_ATQENABLE_M BIT(31)
70 #define PF_SB_ARQLEN_ARQVFE_M BIT(28)
72 #define PF_SB_ARQLEN_ARQOVFL_M BIT(29)
74 #define PF_SB_ARQLEN_ARQCRIT_M BIT(30)
76 #define PF_SB_ARQLEN_ARQENABLE_M BIT(31)
93 #define PF_SB_ATQLEN_ATQVFE_M BIT(28)
95 #define PF_SB_ATQLEN_ATQOVFL_M BIT(29)
97 #define PF_SB_ATQLEN_ATQCRIT_M BIT(30)
99 #define PF_SB_ATQLEN_ATQENABLE_M BIT(31)
111 #define GL_PREEXT_L2_PMASK0(_i) (0x0020F0FC + ((_i) * 4))
112 #define GL_PREEXT_L2_PMASK1(_i) (0x0020F108 + ((_i) * 4))
113 #define GLFLXP_RXDID_FLAGS(_i, _j) (0x0045D000 + ((_i) * 4 + (_j) * 256))
116 #define GLFLXP_RXDID_FLX_WRD_0(_i) (0x0045c800 + ((_i) * 4))
121 #define GLFLXP_RXDID_FLX_WRD_1(_i) (0x0045c900 + ((_i) * 4))
126 #define GLFLXP_RXDID_FLX_WRD_2(_i) (0x0045ca00 + ((_i) * 4))
131 #define GLFLXP_RXDID_FLX_WRD_3(_i) (0x0045cb00 + ((_i) * 4))
136 #define QRXFLXP_CNTXT(_QRX) (0x00480000 + ((_QRX) * 4))
141 #define QRXFLXP_CNTXT_TS_M BIT(11)
142 #define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S 4
143 #define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M ICE_M(0x3, 4)
145 #define GLGEN_GPIO_CTL(_i) (0x000880C8 + ((_i) * 4))
146 #define GLGEN_GPIO_CTL_PIN_DIR_M BIT(4)
157 #define GLGEN_RTRIG_CORER_M BIT(0)
158 #define GLGEN_RTRIG_GLOBR_M BIT(1)
161 #define GLGEN_SWITCH_MODE_CONFIG_25X4_QUAD_M BIT(2)
162 #define GLGEN_VFLRSTAT(_i) (0x00093A04 + ((_i) * 4))
164 #define PFGEN_CTRL_PFSWR_M BIT(0)
167 #define VFGEN_RSTAT(_VF) (0x00074000 + ((_VF) * 4))
168 #define VPGEN_VFRSTAT(_VF) (0x00090800 + ((_VF) * 4))
169 #define VPGEN_VFRSTAT_VFRD_M BIT(0)
170 #define VPGEN_VFRTRIG(_VF) (0x00090000 + ((_VF) * 4))
171 #define VPGEN_VFRTRIG_VFSWR_M BIT(0)
173 #define GLINT_CTL_DIS_AUTOMASK_M BIT(0)
184 #define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4))
185 #define GLINT_DYN_CTL_INTENA_M BIT(0)
186 #define GLINT_DYN_CTL_CLEARPBA_M BIT(1)
187 #define GLINT_DYN_CTL_SWINT_TRIG_M BIT(2)
192 #define GLINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24)
195 #define GLINT_DYN_CTL_WB_ON_ITR_M BIT(30)
196 #define GLINT_DYN_CTL_INTENA_MSK_M BIT(31)
197 #define GLINT_ITR(_i, _INT) (0x00154000 + ((_i) * 8192 + (_INT) * 4))
198 #define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4))
199 #define GLINT_RATE_INTRL_ENA_M BIT(6)
200 #define GLINT_VECT2FUNC(_INT) (0x00162000 + ((_INT) * 4))
206 #define GLINT_VECT2FUNC_IS_PF_M BIT(16)
213 #define PFINT_FW_CTL_CAUSE_ENA_M BIT(30)
218 #define PFINT_MBX_CTL_CAUSE_ENA_M BIT(30)
220 #define PFINT_OICR_TSYN_TX_M BIT(11)
221 #define PFINT_OICR_TSYN_EVNT_M BIT(12)
222 #define PFINT_OICR_ECC_ERR_M BIT(16)
223 #define PFINT_OICR_MAL_DETECT_M BIT(19)
224 #define PFINT_OICR_GRST_M BIT(20)
225 #define PFINT_OICR_PCI_EXCEPTION_M BIT(21)
226 #define PFINT_OICR_HMC_ERR_M BIT(26)
227 #define PFINT_OICR_PE_PUSH_M BIT(27)
228 #define PFINT_OICR_PE_CRITERR_M BIT(28)
229 #define PFINT_OICR_VFLR_M BIT(29)
230 #define PFINT_OICR_SWINT_M BIT(31)
235 #define PFINT_OICR_CTL_CAUSE_ENA_M BIT(30)
239 #define PFINT_SB_CTL_CAUSE_ENA_M BIT(30)
241 #define QINT_RQCTL(_QRX) (0x00150000 + ((_QRX) * 4))
246 #define QINT_RQCTL_CAUSE_ENA_M BIT(30)
247 #define QINT_TQCTL(_DBQM) (0x00140000 + ((_DBQM) * 4))
252 #define QINT_TQCTL_CAUSE_ENA_M BIT(30)
253 #define VPINT_ALLOC(_VF) (0x001D1000 + ((_VF) * 4))
258 #define VPINT_ALLOC_VALID_M BIT(31)
259 #define VPINT_ALLOC_PCI(_VF) (0x0009D000 + ((_VF) * 4))
264 #define VPINT_ALLOC_PCI_VALID_M BIT(31)
265 #define VPINT_MBX_CTL(_VSI) (0x0016A000 + ((_VSI) * 4))
266 #define VPINT_MBX_CTL_CAUSE_ENA_M BIT(30)
268 #define QRX_CONTEXT(_i, _QRX) (0x00280000 + ((_i) * 8192 + (_QRX) * 4))
269 #define QRX_CTRL(_QRX) (0x00120000 + ((_QRX) * 4))
272 #define QRX_CTRL_QENA_REQ_M BIT(0)
274 #define QRX_CTRL_QENA_STAT_M BIT(2)
275 #define QRX_ITR(_QRX) (0x00292000 + ((_QRX) * 4))
276 #define QRX_TAIL(_QRX) (0x00290000 + ((_QRX) * 4))
280 #define VPLAN_RX_QBASE(_VF) (0x00072000 + ((_VF) * 4))
285 #define VPLAN_RXQ_MAPENA(_VF) (0x00073000 + ((_VF) * 4))
286 #define VPLAN_RXQ_MAPENA_RX_ENA_M BIT(0)
287 #define VPLAN_TX_QBASE(_VF) (0x001D1800 + ((_VF) * 4))
292 #define VPLAN_TXQ_MAPENA(_VF) (0x00073800 + ((_VF) * 4))
293 #define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0)
300 #define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
310 #define GL_MDET_RX_VALID_M BIT(31)
314 #define GL_MDET_TX_PQM_VF_NUM_S 4
315 #define GL_MDET_TX_PQM_VF_NUM_M ICE_M(0xFF, 4)
320 #define GL_MDET_TX_PQM_VALID_M BIT(31)
322 ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MDET_TX_TCLAN : \
334 #define GL_MDET_TX_TCLAN_VALID_M BIT(31)
336 #define PF_MDET_RX_VALID_M BIT(0)
338 #define PF_MDET_TX_PQM_VALID_M BIT(0)
340 ((hw)->mac_type == ICE_MAC_E830 ? E830_PF_MDET_TX_TCLAN : \
344 #define PF_MDET_TX_TCLAN_VALID_M BIT(0)
345 #define VP_MDET_RX(_VF) (0x00294400 + ((_VF) * 4))
346 #define VP_MDET_RX_VALID_M BIT(0)
347 #define VP_MDET_TX_PQM(_VF) (0x002D2000 + ((_VF) * 4))
348 #define VP_MDET_TX_PQM_VALID_M BIT(0)
349 #define VP_MDET_TX_TCLAN(_VF) (0x000FB800 + ((_VF) * 4))
350 #define VP_MDET_TX_TCLAN_VALID_M BIT(0)
351 #define VP_MDET_TX_TDPU(_VF) (0x00040000 + ((_VF) * 4))
352 #define VP_MDET_TX_TDPU_VALID_M BIT(0)
356 #define GL_MNG_FWSM_FW_LOADING_M BIT(30)
358 #define GLNVM_FLA_LOCKED_M BIT(6)
363 #define GLNVM_ULD_PCIER_DONE_M BIT(0)
364 #define GLNVM_ULD_PCIER_DONE_1_M BIT(1)
365 #define GLNVM_ULD_CORER_DONE_M BIT(3)
366 #define GLNVM_ULD_GLOBR_DONE_M BIT(4)
367 #define GLNVM_ULD_POR_DONE_M BIT(5)
368 #define GLNVM_ULD_POR_DONE_1_M BIT(8)
369 #define GLNVM_ULD_PCIER_DONE_2_M BIT(9)
370 #define GLNVM_ULD_PE_DONE_M BIT(10)
372 #define GLPCI_CNF2_CACHELINE_SIZE_M BIT(1)
395 #define GLQF_FDINSET(_i, _j) (0x00412000 + ((_i) * 4 + (_j) * 512))
396 #define GLQF_FDMASK(_i) (0x00410800 + ((_i) * 4))
402 #define GLQF_FDMASK_SEL(_i) (0x00410400 + ((_i) * 4))
403 #define GLQF_FDSWAP(_i, _j) (0x00413000 + ((_i) * 4 + (_j) * 512))
404 #define GLQF_HMASK(_i) (0x0040FC00 + ((_i) * 4))
410 #define GLQF_HMASK_SEL(_i) (0x00410000 + ((_i) * 4))
413 #define GLQF_HSYMM(_i, _j) (0x0040F000 + ((_i) * 4 + (_j) * 512))
414 #define GLQF_HSYMM_REG_SIZE 4
416 #define GLQF_HSYMM_ENABLE_BIT BIT(7)
422 #define PFQF_FD_ENA_FD_ENA_M BIT(0)
474 #define GLV_RDPC(_i) (0x00294C04 + ((_i) * 4))
475 #define GLV_TEPC(_VSI) (0x00312000 + ((_VSI) * 4))
480 #define GLHH_ART_CTL_ACTIVE_M BIT(0)
483 #define GLTSYN_AUX_IN_0(_i) (0x000889D8 + ((_i) * 4))
484 #define GLTSYN_AUX_IN_0_INT_ENA_M BIT(4)
485 #define GLTSYN_AUX_OUT_0(_i) (0x00088998 + ((_i) * 4))
486 #define GLTSYN_AUX_OUT_0_OUT_ENA_M BIT(0)
488 #define GLTSYN_CLKO_0(_i) (0x000889B8 + ((_i) * 4))
491 #define GLTSYN_ENA(_i) (0x00088808 + ((_i) * 4))
492 #define GLTSYN_ENA_TSYN_ENA_M BIT(0)
493 #define GLTSYN_EVNT_H_0(_i) (0x00088970 + ((_i) * 4))
494 #define GLTSYN_EVNT_L_0(_i) (0x00088968 + ((_i) * 4))
495 #define GLTSYN_HHTIME_H(_i) (0x00088900 + ((_i) * 4))
496 #define GLTSYN_HHTIME_L(_i) (0x000888F8 + ((_i) * 4))
497 #define GLTSYN_INCVAL_H(_i) (0x00088920 + ((_i) * 4))
498 #define GLTSYN_INCVAL_L(_i) (0x00088918 + ((_i) * 4))
499 #define GLTSYN_SHADJ_H(_i) (0x00088910 + ((_i) * 4))
500 #define GLTSYN_SHADJ_L(_i) (0x00088908 + ((_i) * 4))
501 #define GLTSYN_SHTIME_0(_i) (0x000888E0 + ((_i) * 4))
502 #define GLTSYN_SHTIME_H(_i) (0x000888F0 + ((_i) * 4))
503 #define GLTSYN_SHTIME_L(_i) (0x000888E8 + ((_i) * 4))
504 #define GLTSYN_STAT(_i) (0x000888C0 + ((_i) * 4))
505 #define GLTSYN_STAT_EVENT0_M BIT(0)
506 #define GLTSYN_STAT_EVENT1_M BIT(1)
507 #define GLTSYN_STAT_EVENT2_M BIT(2)
509 #define GLTSYN_TGT_H_0(_i) (0x00088930 + ((_i) * 4))
510 #define GLTSYN_TGT_L_0(_i) (0x00088928 + ((_i) * 4))
511 #define GLTSYN_TIME_0(_i) (0x000888C8 + ((_i) * 4))
512 #define GLTSYN_TIME_H(_i) (0x000888D8 + ((_i) * 4))
513 #define GLTSYN_TIME_L(_i) (0x000888D0 + ((_i) * 4))
515 #define PFHH_SEM_BUSY_M BIT(0)
517 #define PFTSYN_SEM_BUSY_M BIT(0)
518 #define VSIQF_FD_CNT(_VSI) (0x00464000 + ((_VSI) * 4))
525 #define VSIQF_FD_SIZE(_VSI) (0x00462000 + ((_VSI) * 4))
528 #define PFPM_APM_APME_M BIT(0)
530 #define PFPM_WUFC_MAG_M BIT(1)
532 #define PFPM_WUS_LNKC_M BIT(0)
533 #define PFPM_WUS_MAG_M BIT(1)
534 #define PFPM_WUS_MNG_M BIT(3)
535 #define PFPM_WUS_FW_RST_WK_M BIT(31)
540 #define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4))
541 #define VFINT_DYN_CTLN_CLEARPBA_M BIT(1)