rtlwifi/rtl8188ee/pwrseq.h

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2013  Realtek Corporation.*/
8 /* Check document WM-20110607-Paul-RTL8188EE_Power_Architecture-R02.vsd
10  *	0: POFF--Power Off
11  *	1: PDN--Power Down
12  *	2: CARDEMU--Card Emulation
13  *	3: ACT--Active Mode
14  *	4: LPS--Low Power State
15  *	5: SUS--Suspend
46 	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)		\
49 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0		\
52 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)			\
55 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0			\
58 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0		\
61 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)			\
64 	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0			\
67 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0			\
70 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)			\
78 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)			\
81 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)			\
84 	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0			\
90 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)		\
93 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4)	\
97 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT(7)			\
101 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0			\
105 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)			\
106 	/*Set USB suspend enable local register  0xfe10[4]=1 */},	\
108 	PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)		\
111 	PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0			\
116 	PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0			\
119 	PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)		\
122 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0		\
127 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)			\
131 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)	\
139 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0			\
142 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)			\
143 	/*Set USB suspend enable local register  0xfe10[4]=1 */},	\
145 	PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)		\
148 	PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0			\
153 	PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0			\
156 	PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)		\
159 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0		\
164 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0/* 0x04[16] = 0*/},	\
166 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)			\
171 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0/* 0x04[15] = 0*/},
190 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0			\
199 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0			\
202 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)			\
220 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0			\
221 	/*.	0x08[4] = 0		 switch TSF to 40M*/},		\
223 	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0			\
226 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0		\
229 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)			\
235 	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)	\