Lines Matching +full:4 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
18 #define TW5864_EMU_EN_DDR BIT(0)
19 /* Enable bit for Inter module */
20 #define TW5864_EMU_EN_ME BIT(1)
21 /* Enable bit for Sensor Interface module */
22 #define TW5864_EMU_EN_SEN BIT(2)
23 /* Enable bit for Host Burst Access */
24 #define TW5864_EMU_EN_BHOST BIT(3)
25 /* Enable bit for Loop Filter module */
26 #define TW5864_EMU_EN_LPF BIT(4)
27 /* Enable bit for PLBK module */
28 #define TW5864_EMU_EN_PLBK BIT(5)
38 #define TW5864_DSP_FRAME_TYPE_D1 BIT(6)
45 #define TW5864_VLC_SLICE_END BIT(0)
47 #define TW5864_MAS_SLICE_END BIT(4)
49 #define TW5864_START_NSLICE BIT(15)
52 * [15:0] Two bit for each channel (channel 0 ~ 7). Each two bits are the buffer
74 #define TW5864_DSP_CODEC_MODE BIT(0)
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
81 * 0 4CIF in 1 MB
84 #define TW5864_CIF_MAP_MD BIT(6)
89 #define TW5864_HD1_MAP_MD BIT(7)
91 #define TW5864_VLC_VLD BIT(8)
93 #define TW5864_MV_VECT_VLD BIT(9)
95 #define TW5864_MV_FLAG_VLD BIT(10)
101 /* Org Buffer Base for Chroma (default 4) */
103 /* Maximum Number of Buffers (default 4) */
115 /* Ref Buffer Base for Chroma (default 4) */
117 /* Maximum Number of Buffers (default 4) */
147 /* DDR-DPR Burst Read Enable */
148 #define TW5864_DDR_BRST_EN BIT(13)
154 #define TW5864_DDR_AB_SEL BIT(14)
157 * 0 Single R/W Access (Host <-> DDR)
158 * 1 Burst R/W Access (Host <-> DPR)
160 #define TW5864_DDR_MODE BIT(15)
174 * [15:0]: ENC_BUF_PTR_REC[31:16] Two bit for each channel (channel 8 ~ 15).
190 * [15:0] Reset Current MV Flag Status Pointer for Channel n (one bit each)
196 * Inter_Mode Start. 2-nd bit? A guess. Missing in datasheet. Without this bit
199 #define TW5864_DSP_INTER_ST BIT(1)
201 #define TW5864_DI_EN BIT(2)
203 * De-interlacer Mode
205 * 0 Normal Un-Shuffled Frame
207 #define TW5864_DI_MD BIT(3)
210 * 11: Un-used
211 * 10: down-sample to 1/4
212 * 01: down-sample to 1/2
213 * 00: down-sample disabled
215 #define TW5864_DSP_DWN_X (3 << 4)
218 * 11: Un-used
219 * 10: down-sample to 1/4
220 * 01: down-sample to 1/2
221 * 00: down-sample disabled
228 #define TW5864_DUAL_STR BIT(8)
240 * Skip Offset Enable bit
251 #define TW5864_QPEL_EN BIT(0)
253 #define TW5864_HPEL_EN BIT(1)
255 #define TW5864_ME_EN BIT(2)
257 #define TW5864_INTRA_EN BIT(3)
259 #define TW5864_SKIP_EN BIT(4)
289 /* OSD enable bit for each channel */
292 /* 0x0280 ~ 0x029c - Motion Vector for 1st 4x4 Block, e.g., 80 (X), 84 (Y) */
294 /* 0x02a0 ~ 0x02bc - Motion Vector for 2nd 4x4 Block, e.g., A0 (X), A4 (Y) */
296 /* 0x02c0 ~ 0x02dc - Motion Vector for 3rd 4x4 Block, e.g., C0 (X), C4 (Y) */
298 /* 0x02e0 ~ 0x02fc - Motion Vector for 4th 4x4 Block, e.g., E0 (X), E4 (Y) */
311 * [6:4]
312 * 0x5 Only 4x4
314 * 0x7 16x16 & 4x4
317 #define TW5864_DSP_INTRA_MODE_SHIFT 4
318 #define TW5864_DSP_INTRA_MODE_MASK (7 << 4)
336 /* 0x0800 ~ 0x09ff - Quantization TABLE Values */
341 (0x0c00 | (channel << 4) | (frame << 2))
348 #define TW5864_PROG_A BIT(0)
353 #define TW5864_PROG_B BIT(1)
358 #define TW5864_FRAME BIT(2)
360 * 0 4CIF in bus n
361 * 1 1D1 + 4 CIF in bus n
365 /* Bus 1 goes in TW5864_FRAME_BUS1 in [4:0] */
368 /* Bus 3 goes in TW5864_FRAME_BUS2 in [4:0] */
369 /* Bus 4 goes in TW5864_FRAME_BUS2 in [12:8] */
378 * 0x15f: 4 CIF
382 * 0x15f: 4 CIF
386 * 0x11f: 4CIF (PAL)
389 * 0x0ef: 4CIF (NTSC)
393 * 0x11f: 4CIF (PAL)
396 * 0x0ef: 4CIF (NTSC)
422 * Swap byte order of VLC stream in d-word.
426 #define TW5864_VLC_BYTE_SWP BIT(6)
428 #define TW5864_VLC_ADD03_EN BIT(7)
429 /* Number of bit for VLC bit Align */
437 #define TW5864_VLC_INF_SEL BIT(13)
439 #define TW5864_VLC_OVFL_CNTL BIT(14)
444 #define TW5864_VLC_PCI_SEL BIT(15)
449 #define TW5864_VLC_A03_DISAB BIT(16)
451 * Status of VLC stream in DDR (one bit for each buffer)
458 /* Total number of bit in the slice */
460 /* Total number of bit in the residue */
466 #define TW5864_VLC_BK0_FULL BIT(0)
468 #define TW5864_VLC_BK1_FULL BIT(1)
470 #define TW5864_VLC_END_SLICE BIT(2)
472 #define TW5864_DSP_RD_OF BIT(3)
474 #define TW5864_VLC_STREAM_LEN_SHIFT 4
475 #define TW5864_VLC_STREAM_LEN_MASK (0x1ff << 4)
490 #define TW5864_VLC_RD_MEM BIT(0)
495 #define TW5864_VLC_RD_BRST BIT(1)
497 /* 0x2000 ~ 0x2ffc - H264 Stream Memory Map */
499 * A word is 4 bytes. I.e.,
507 #define TW5864_VLC_STREAM_MEM(offset) (TW5864_VLC_STREAM_MEM_START + 4 * offset)
509 /* 0x4000 ~ 0x4ffc - Audio Register Map */
516 #define TW5864_ADPCM_DEC BIT(0)
518 #define TW5864_ADPCM_IN_DATA BIT(1)
520 #define TW5864_ADPCM_ENC BIT(2)
524 /* Record path PCM Audio enable bit for each channel */
527 #define TW5864_SPK_ORG_EN BIT(16)
529 * 0 16bit
530 * 1 8bit
532 #define TW5864_AD_BIT_MODE BIT(17)
549 #define TW5864_TEST_ADLOOP_EN BIT(30)
554 #define TW5864_AUD_MODE BIT(31)
558 /* Record path ADPCM audio channel enable, one bit for each */
561 #define TW5864_SPK_ADPCM_EN BIT(16)
568 * Bit[2:0] ch0
569 * Bit[5:3] ch1
570 * Bit[8:6] ch2
571 * Bit[11:9] ch3
572 * Bit[14:12] ch4
573 * Bit[17:15] ch5
574 * Bit[20:18] ch6
575 * Bit[23:21] ch7
576 * Bit[26:24] ch8
577 * Bit[29:27] ch9
578 * Bit[32:30] ch10
579 * Bit[35:33] ch11
580 * Bit[38:36] ch12
581 * Bit[41:39] ch13
582 * Bit[44:42] ch14
583 * Bit[47:45] ch15
584 * Bit[50:48] ch16
598 /* [3:0] rd ch0, [7:4] rd ch1, [11:8] wr ch0, [15:12] wr ch1 */
603 * Bit[3:0] ch0
604 * Bit[7:4] ch1
605 * Bit[11:8] ch2
606 * Bit[15:12] ch3
607 * Bit[19:16] ch4
608 * Bit[23:20] ch5
609 * Bit[27:24] ch6
610 * Bit[31:28] ch7
611 * Bit[35:32] ch8
612 * Bit[39:36] ch9
613 * Bit[43:40] ch10
614 * Bit[47:44] ch11
615 * Bit[51:48] ch12
616 * Bit[55:52] ch13
617 * Bit[59:56] ch14
618 * Bit[63:60] ch15
619 * Bit[67:64] ch16
642 * or ADPCM(1) audio data sent to PC. One bit for each channel
646 * Audio flow control mode selection bit.
651 #define TW5864_PCI_FLOW_EN BIT(16)
653 * When PCI_FLOW_EN is set, PCI need to toggle this bit to send an audio frame
656 #define TW5864_PCI_AUD_FRM_EN BIT(17)
669 #define TW5864_SYNC_CFG BIT(7)
674 #define TW5864_SYNC_ADR_EDGE BIT(0)
687 #define TW5864_VLC_OUT_EDGE BIT(3)
699 * The system / DDR clock (166 MHz) is generated with an on-chip system clock
712 /* [2:0]: SYSPLL_M[10:8], [7:3]: SYSPLL_N[4:0] */
720 * [1:0]: SYSPLL_N[6:5], [3:2]: SYSPLL_P, [4]: SYSPLL_IREF, [7:5]: SYSPLL_CP_SEL
732 #define TW5864_SYSPLL_IREF BIT(4)
736 * 1 4 uA
739 * 4 39 uA
748 * [1:0]: SYSPLL_VCO, [3:2]: SYSPLL_LP_X8, [5:4]: SYSPLL_ICP_SEL,
770 #define TW5864_SYSPLL_ICP_SEL_SHIFT 4
778 #define TW5864_SYSPLL_ICP_SEL (0x03 << 4)
784 #define TW5864_SYSPLL_LPF_5PF BIT(6)
790 #define TW5864_SYSPLL_ED_SEL BIT(7)
792 /* [0]: SYSPLL_RST, [4]: SYSPLL_PD */
796 #define TW5864_SYSPLL_RST BIT(0)
798 #define TW5864_SYSPLL_PD BIT(4)
804 * Become valid after sync to the xtal clock domain. This bit is set only if
805 * LOAD register bit is also set to 1.
807 #define TW5864_SRST BIT(0)
811 * LOAD register bit is also set to 1.
813 #define TW5864_SYSPLL_CFG BIT(2)
817 * the LOAD register bit is also set to 1.
819 #define TW5864_SPLL_CFG BIT(4)
821 * Set this bit to latch the SRST, SYSPLL_CFG, SPLL_CFG setting into the xtal
822 * clock domain to restart the PLL. This bit is self cleared.
824 #define TW5864_LOAD BIT(3)
829 /* 0x8800 ~ 0x88fc - Interrupt Register Map */
848 * 1 High level or pos-edge is assertion
849 * 0 Low level or neg-edge is assertion
862 * Bit[0]: VLC 4k RAM interrupt
863 * Bit[1]: BURST DDR RAM interrupt
864 * Bit[2]: MV DSP interrupt
865 * Bit[3]: video lost interrupt
866 * Bit[4]: gpio 0 interrupt
867 * Bit[5]: gpio 1 interrupt
868 * Bit[6]: gpio 2 interrupt
869 * Bit[7]: gpio 3 interrupt
870 * Bit[8]: gpio 4 interrupt
871 * Bit[9]: gpio 5 interrupt
872 * Bit[10]: gpio 6 interrupt
873 * Bit[11]: gpio 7 interrupt
874 * Bit[12]: JPEG interrupt
875 * Bit[13:15]: Reserved
880 * Bit[0]: Reserved
881 * Bit[1]: VLC done interrupt
882 * Bit[2]: Reserved
883 * Bit[3]: AD Vsync interrupt
884 * Bit[4]: Preview eof interrupt
885 * Bit[5]: Preview overflow interrupt
886 * Bit[6]: Timer interrupt
887 * Bit[7]: Reserved
888 * Bit[8]: Audio eof interrupt
889 * Bit[9]: I2C done interrupt
890 * Bit[10]: AD interrupt
891 * Bit[11:15]: Reserved
896 #define TW5864_INTR_VLC_RAM BIT(0)
897 #define TW5864_INTR_BURST BIT(1)
898 #define TW5864_INTR_MV_DSP BIT(2)
899 #define TW5864_INTR_VIN_LOST BIT(3)
901 #define TW5864_INTR_GPIO(n) (1 << (4 + n))
902 #define TW5864_INTR_JPEG BIT(12)
903 #define TW5864_INTR_VLC_DONE BIT(17)
904 #define TW5864_INTR_AD_VSYNC BIT(19)
905 #define TW5864_INTR_PV_EOF BIT(20)
906 #define TW5864_INTR_PV_OVERFLOW BIT(21)
907 #define TW5864_INTR_TIMER BIT(22)
908 #define TW5864_INTR_AUD_EOF BIT(24)
909 #define TW5864_INTR_I2C_DONE BIT(25)
910 #define TW5864_INTR_AD BIT(26)
912 /* 0x9000 ~ 0x920c - Video Capture (VIF) Register Map */
941 * 0 Max 4 channels
954 * [4:0] H264EN_RATE_MAX_LINE_0
959 * [4:0] H264EN_RATE_MAX_LINE_2
992 * H264EN_BUSm_MAP_CHn The 16-to-1 MUX configuration register for each encoding
1012 /* 0xa000 ~ 0xa8ff - DDR Controller Register Map */
1030 * default is 4"hf
1036 * period, default is 4"h2
1038 #define TW5864_TCD_CNT_MAX_SHIFT 4
1039 #define TW5864_TCD_CNT_MAX (0x0f << 4)
1040 /* Twr value, write recovery time, default is 4"h3 */
1046 * availability of the first bit of output data, default is 3
1068 * 1 DDR self-test mode
1070 #define TW5864_MASTER_MODE BIT(0)
1072 * 0 DDR self-test single read/write
1073 * 1 DDR self-test burst read/write
1075 #define TW5864_SINGLE_PROC BIT(1)
1077 * 0 DDR self-test write command
1078 * 1 DDR self-test read command
1080 #define TW5864_WRITE_FLAG BIT(2)
1081 #define TW5864_DATA_MODE_SHIFT 4
1088 #define TW5864_DATA_MODE (0x3 << 4)
1090 /* [7:0] The maximum data of one burst in DDR self-test mode */
1092 /* [15:0] The maximum burst counter (bit 15~0) in DDR self-test mode */
1094 /* The maximum burst counter (bit 31~16) in DDR self-test mode */
1096 /* [0]: Start one DDR self-test */
1098 /* The maximum error counter (bit 15 ~ 0) in DDR self-test */
1103 /* The maximum error counter (bit 30 ~ 16) in DDR self-test */
1105 /* DDR self-test end flag */
1114 /* 0xb004 ~ 0xb018 - HW version/ARB12 Register Map */
1121 #define TW5864_AUD_DATA_IN_ENB BIT(0)
1123 #define TW5864_AUD_ENC_REQ_ENB BIT(1)
1125 #define TW5864_AUD_DEC_REQ0_ENB BIT(2)
1127 #define TW5864_AUD_DEC_REQ1_ENB BIT(3)
1129 #define TW5864_VLC_STRM_REQ_ENB BIT(4)
1131 #define TW5864_DVM_MV_REQ_ENB BIT(5)
1133 #define TW5864_MVD_REQ_ENB BIT(6)
1135 #define TW5864_MVD_TMP_REQ_ENB BIT(7)
1137 #define TW5864_JPEG_REQ_ENB BIT(8)
1139 #define TW5864_MV_FLAG_REQ_ENB BIT(9)
1144 #define TW5864_ARB12_ENB BIT(15)
1148 /* 0xb800 ~ 0xb80c - Indirect Access Register Map */
1164 * (4) Read IND_DATA from 0xb804 ~ 0xb807
1170 /* Wait until this bit is "0" before using indirect access */
1171 #define TW5864_BUSY BIT(31)
1172 /* Activate the indirect access. This bit is self cleared */
1173 #define TW5864_ENABLE BIT(25)
1175 #define TW5864_RW BIT(24)
1180 /* 0xc000 ~ 0xc7fc - Preview Register Map */
1195 /* 0xc800 ~ 0xc804 - JPEG Capture Register Map */
1197 /* 0xd000 ~ 0xd0fc - JPEG Control Register Map */
1200 /* 0xe000 ~ 0xfc04 - Motion Vector Register Map */
1205 #define TW5864_ME_MV_VEC(offset) (TW5864_ME_MV_VEC_START + 4 * offset)
1210 #define TW5864_MV_BK0_FULL BIT(0)
1212 #define TW5864_MV_BK1_FULL BIT(1)
1214 #define TW5864_MV_EOF BIT(2)
1216 #define TW5864_MV_DSP_INTR BIT(3)
1218 #define TW5864_DSP_WR_OF BIT(4)
1222 /* The configured status bit written into bit 15 of 0xfc04 */
1223 #define TW5864_MPI_DDR_SEL BIT(13)
1232 #define TW5864_MPI_DDR_SEL2 BIT(15)
1234 /* 0x18000 ~ 0x181fc - PCI Master/Slave Control Map */
1238 #define TW5864_VLC_DONE_INTR BIT(1)
1240 #define TW5864_AD_VSYNC_INTR BIT(3)
1242 #define TW5864_PREV_EOF_INTR BIT(4)
1244 #define TW5864_PREV_OVERFLOW_INTR BIT(5)
1246 #define TW5864_TIMER_INTR BIT(6)
1248 #define TW5864_AUDIO_EOF_INTR BIT(8)
1250 #define TW5864_IIC_DONE_INTR BIT(24)
1252 #define TW5864_AD_INTR_REG BIT(25)
1257 #define TW5864_PCI_MAST_ENB BIT(0)
1261 #define TW5864_AD_MAST_ENB BIT(3)
1263 #define TW5864_PREV_MAST_ENB BIT(4)
1265 #define TW5864_PREV_OVERFLOW_ENB BIT(5)
1267 #define TW5864_TIMER_INTR_ENB BIT(6)
1269 #define TW5864_JPEG_MAST_ENB BIT(7)
1274 #define TW5864_IIC_INTR_ENB BIT(24)
1276 #define TW5864_AD_INTR_ENB BIT(25)
1278 #define TW5864_PCI_TAR_BURST_ENB BIT(26)
1280 #define TW5864_PCI_VLC_BURST_ENB BIT(27)
1282 #define TW5864_PCI_DDR_BURST_ENB BIT(28)
1301 #define TW5864_PCI_VLC_INTR_ENB BIT(1)
1303 #define TW5864_PCI_PREV_INTR_ENB BIT(4)
1305 #define TW5864_PCI_PREV_OF_INTR_ENB BIT(5)
1307 #define TW5864_PCI_JPEG_INTR_ENB BIT(7)
1309 #define TW5864_PCI_AUD_INTR_ENB BIT(8)
1312 * Every channel of preview and audio have ping-pong buffers in system memory,
1332 #define TW5864_IIC_RW BIT(16)
1338 * bit to 1. Then poll this bit, value 1 indicate iic transaction have
1341 #define TW5864_IIC_DONE BIT(24)
1346 #define TW5864_APP_SOFT_RST BIT(0)
1388 * 2 4ms
1407 /* 0x80000 ~ 0x87fff - DDR Burst RW Register Map */
1411 /* Length of 32-bit data burst */
1418 #define TW5864_BRST_RW BIT(16)
1419 /* Begin a new DDR Burst. This bit is self cleared */
1420 #define TW5864_NEW_BRST_CMD BIT(17)
1422 #define TW5864_BRST_END BIT(24)
1424 #define TW5864_SING_ERR_INTR BIT(25)
1426 #define TW5864_BRST_ERR_INTR BIT(26)
1428 #define TW5864_BRST_END_INTR BIT(27)
1430 #define TW5864_SINGLE_ERR BIT(28)
1432 #define TW5864_SINGLE_BUSY BIT(29)
1434 #define TW5864_BRST_ERR BIT(30)
1436 #define TW5864_BRST_BUSY BIT(31)
1438 /* [27:0] DDR Access Address. Bit [1:0] has to be 0 */
1440 /* DDR Access Internal Buffer Address. Bit [1:0] has to be 0 */
1444 /* 0x84000 - 0x87ffc */
1454 /* Read-only register */
1462 #define TW5864_INDIR_VIN_0_VDLOSS BIT(7)
1467 #define TW5864_INDIR_VIN_0_HLOCK BIT(6)
1469 * 1 Sub-carrier PLL is locked to the incoming video source.
1470 * 0 Sub-carrier PLL is not locked.
1472 #define TW5864_INDIR_VIN_0_SLOCK BIT(5)
1477 #define TW5864_INDIR_VIN_0_FLD BIT(4)
1482 #define TW5864_INDIR_VIN_0_VLOCK BIT(3)
1487 #define TW5864_INDIR_VIN_0_MONO BIT(1)
1494 #define TW5864_INDIR_VIN_0_DET50 BIT(0)
1497 /* VCR signal indicator. Read-only. */
1498 #define TW5864_INDIR_VIN_1_VCR BIT(7)
1499 /* Weak signal indicator 2. Read-only. */
1500 #define TW5864_INDIR_VIN_1_WKAIR BIT(6)
1501 /* Weak signal indicator controlled by WKTH. Read-only. */
1502 #define TW5864_INDIR_VIN_1_WKAIR1 BIT(5)
1505 * 0 = Non-standard signal
1506 * Read-only
1508 #define TW5864_INDIR_VIN_1_VSTD BIT(4)
1510 * 1 = Non-interlaced signal
1512 * Read-only
1514 #define TW5864_INDIR_VIN_1_NINTL BIT(3)
1537 #define TW5864_INDIR_VIN_6_VDELAY_XY_HI BIT(4)
1538 #define TW5864_INDIR_VIN_6_VACTIVE_XY_HI BIT(5)
1541 * HDELAY_XY This 10bit register defines the starting location of horizontal
1545 * HACTIVE_XY This 10bit register defines the number of horizontal active pixel
1549 * VDELAY_XY This 9bit register defines the starting location of vertical
1553 * VACTIVE_XY This 9bit register defines the number of vertical active lines
1559 * value from +36o (7Fh) to -36o (80h) with an increment of 2.8o. The 2 LSB has
1569 * This bit controls the center frequency of the peaking filter.
1574 #define TW5864_INDIR_VIN_8_SCURVE BIT(7)
1579 #define TW5864_INDIR_VIN_8_CTI_SHIFT 4
1580 #define TW5864_INDIR_VIN_8_CTI (0x03 << 4)
1598 * These bits control the brightness. They have value of -128 to 127 in 2's
1624 /* Read-only */
1627 /* Macrovision color stripe detection may be un-reliable */
1628 #define TW5864_INDIR_VIN_D_CSBAD BIT(3)
1630 #define TW5864_INDIR_VIN_D_MCVSN BIT(2)
1632 #define TW5864_INDIR_VIN_D_CSTRIPE BIT(1)
1634 * This bit is valid only when color stripe protection is detected, i.e. if
1639 #define TW5864_INDIR_VIN_D_CTYPE2 BIT(0)
1641 /* Read-only */
1645 * Read-only.
1649 #define TW5864_INDIR_VIN_E_DETSTUS BIT(7)
1656 * 4 PAL (M)
1661 #define TW5864_INDIR_VIN_E_STDNOW_SHIFT 4
1662 #define TW5864_INDIR_VIN_E_STDNOW (0x07 << 4)
1669 #define TW5864_INDIR_VIN_E_ATREG BIT(3)
1676 * 4 PAL (M)
1686 * 1 Writing 1 to this bit will manually initiate the auto format detection
1687 * process. This bit is a self-clearing bit
1690 #define TW5864_INDIR_VIN_F_ATSTART BIT(7)
1692 #define TW5864_INDIR_VIN_F_PAL60EN BIT(6)
1694 #define TW5864_INDIR_VIN_F_PALCNEN BIT(5)
1696 #define TW5864_INDIR_VIN_F_PALMEN BIT(4)
1698 #define TW5864_INDIR_VIN_F_NTSC44EN BIT(3)
1700 #define TW5864_INDIR_VIN_F_SECAMEN BIT(2)
1702 #define TW5864_INDIR_VIN_F_PALBEN BIT(1)
1704 #define TW5864_INDIR_VIN_F_NTSCEN BIT(0)
1708 /* Use falling edge to sample VD1-VD4 from 54 MHz to 108 MHz */
1710 #define TW5864_INDIR_VD_108_POL_VD12 BIT(0)
1711 #define TW5864_INDIR_VD_108_POL_VD34 BIT(1)
1723 * 4 0.50
1736 /* [3:0] channel 0, [7:4] channel 1 */
1738 /* [3:0] channel 2, [7:4] channel 3 */
1746 * LAWMD Select u-Law/A-Law/PCM/SB data output format on ADATR and ADATM pin.
1748 * 1 SB (Signed MSB bit in PCM data is inverted) output
1749 * 2 u-Law output
1750 * 3 A-Law output
1759 #define TW5864_INDIR_AIN_MIX_DERATIO BIT(5)
1762 * only for mixing. When n = 4, it enable the mute function of the playback
1774 * ADATP signal is coming from external ADPCM decoder, instead of on-chip ADPCM
1777 #define TW5864_INDIR_AIN_0x0E3_EXT_ADATP BIT(7)
1779 #define TW5864_INDIR_AIN_0x0E3_ACLKPPOLO BIT(6)
1785 #define TW5864_INDIR_AIN_0x0E3_ACLKRPOL BIT(5)
1791 #define TW5864_INDIR_AIN_0x0E3_ACLKPPOLI BIT(4)
1798 #define TW5864_INDIR_AIN_0x0E3_AFAUTO BIT(3)
1805 * 4 48kHz setting
1812 * 8bit I2S Record output mode.
1816 #define TW5864_INDIR_AIN_0x0E4_I2S8MODE BIT(7)
1820 * 1 Almost duty 50-50% clock output on ACLKR pin. If this mode is selected, two
1824 #define TW5864_INDIR_AIN_0x0E4_MASCKMD BIT(6)
1825 /* Playback ACLKP/ASYNP/ADATP input data MSB-LSB swapping */
1826 #define TW5864_INDIR_AIN_0x0E4_PBINSWAP BIT(5)
1832 #define TW5864_INDIR_AIN_0x0E4_ASYNRDLY BIT(4)
1838 #define TW5864_INDIR_AIN_0x0E4_ASYNPDLY BIT(3)
1842 * 1 Add 1 ACLKP clock delay in ADATP input data. This is for left-justified
1845 #define TW5864_INDIR_AIN_0x0E4_ADATPDLY BIT(2)
1847 * Select u-Law/A-Law/PCM/SB data input format on ADATP pin.
1849 * 1 SB (Signed MSB bit in PCM data is inverted) input
1850 * 2 u-Law input
1851 * 3 A-Law input
1869 #define TW5864_INDIR_IN_PIC_WIDTH(channel) (0x200 + 4 * channel)
1870 #define TW5864_INDIR_IN_PIC_HEIGHT(channel) (0x201 + 4 * channel)
1871 #define TW5864_INDIR_OUT_PIC_WIDTH(channel) (0x202 + 4 * channel)
1872 #define TW5864_INDIR_OUT_PIC_HEIGHT(channel) (0x203 + 4 * channel)
1882 * Interrupt status register from the front-end. Write "1" to each bit to clear
1912 * bit 0: interrupt occurs in 0x2d0 & 0x2d8
1913 * bit 1: interrupt occurs in 0x2d1 & 0x2d9
1914 * bit 2: interrupt occurs in 0x2d2 & 0x2da
1915 * bit 3: interrupt occurs in 0x2d3 & 0x2db
1916 * bit 4: interrupt occurs in 0x2d4 & 0x2dc
1917 * bit 5: interrupt occurs in 0x2d5 & 0x2dd
1918 * bit 6: interrupt occurs in 0x2d6 & 0x2de
1919 * bit 7: interrupt occurs in 0x2d7 & 0x2df
1920 * bit 8: interrupt occurs in 0x2e0 & 0x2e8
1921 * bit 9: interrupt occurs in 0x2e1 & 0x2e9
1922 * bit 10: interrupt occurs in 0x2e2 & 0x2ea
1923 * bit 11: interrupt occurs in 0x2e3 & 0x2eb
1936 #define TW5864_INDIR_DETECTION_CTL0_MD_DIS BIT(5)
1942 #define TW5864_INDIR_DETECTION_CTL0_MD_STRB BIT(3)
1948 #define TW5864_INDIR_DETECTION_CTL0_MD_STRB_EN BIT(2)
1965 #define TW5864_INDIR_DETECTION_CTL1_MD_TMPSENS_SHIFT 4
1966 #define TW5864_INDIR_DETECTION_CTL1_MD_TMPSENS (0x0f << 4)
1982 #define TW5864_INDIR_DETECTION_CTL2_MD_REFFLD BIT(7)
2003 * Define the threshold of sub-cell number for motion detection.
2004 * 0 Motion is detected if 1 sub-cell has motion (More sensitive) (default)
2005 * 1 Motion is detected if 2 sub-cells have motion
2006 * 2 Motion is detected if 3 sub-cells have motion
2007 * 3 Motion is detected if 4 sub-cells have motion (Less sensitive)
2032 #define TW5864_INDIR_DETECTION_CTL4_MD_SPSENS_SHIFT 4
2033 #define TW5864_INDIR_DETECTION_CTL4_MD_SPSENS (0x0f << 4)
2049 #define TW5864_INDIR_DETECTION_CTL5_ND_TMPSENS_SHIFT 4
2050 #define TW5864_INDIR_DETECTION_CTL5_ND_TMPSENS (0x0f << 4)
2083 /* 192 bit motion flag of the channel specified by RGR_MOTION_SEL in 0x382 */
2097 /* 192 bit motion mask of the channel specified by MASK_CH_SEL in 0x3fe */
2101 /* [4:0] The channel selection to access masks in 0x3e0 ~ 0x3f7 */
2118 #define TW5864_INDIR_RESET_VD BIT(7)
2119 #define TW5864_INDIR_RESET_DLL BIT(6)
2120 #define TW5864_INDIR_RESET_MUX_CORE BIT(5)
2123 #define TW5864_INDIR_PV_VD_CK_POL_PV(channel) BIT(channel)
2124 #define TW5864_INDIR_PV_VD_CK_POL_VD(channel) BIT(channel + 4)
2131 #define TW5864_INDIR_CLK0_SEL_PV2_SHIFT 4
2132 #define TW5864_INDIR_CLK0_SEL_PV2_MASK (0x3 << 4)