Lines Matching +full:4 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
7 #include "phy-mtk-io.h"
8 #include "phy-mtk-mipi-dsi.h"
11 #define RG_DSI_LDOCORE_EN BIT(0)
12 #define RG_DSI_CKG_LDOOUT_EN BIT(1)
14 #define RG_DSI_LD_IDX_SEL GENMASK(6, 4)
16 #define RG_DSI_DSICLK_FREQ_SEL BIT(10)
17 #define RG_DSI_LPTX_CLMP_EN BIT(11)
24 #define RG_DSI_LNTx_LDOOUT_EN BIT(0)
25 #define RG_DSI_LNTx_CKLANE_EN BIT(1)
26 #define RG_DSI_LNTx_LPTX_IPLUS1 BIT(2)
27 #define RG_DSI_LNTx_LPTX_IPLUS2 BIT(3)
28 #define RG_DSI_LNTx_LPTX_IMINUS BIT(4)
29 #define RG_DSI_LNTx_LPCD_IPLUS BIT(5)
30 #define RG_DSI_LNTx_LPCD_IMINUS BIT(6)
34 #define RG_DSI_LNT_INTR_EN BIT(0)
35 #define RG_DSI_LNT_HS_BIAS_EN BIT(1)
36 #define RG_DSI_LNT_IMP_CAL_EN BIT(2)
37 #define RG_DSI_LNT_TESTMODE_EN BIT(3)
38 #define RG_DSI_LNT_IMP_CAL_CODE GENMASK(7, 4)
40 #define RG_DSI_PAD_TIE_LOW_EN BIT(11)
41 #define RG_DSI_DEBUG_INPUT_EN BIT(12)
45 #define RG_DSI_BG_CORE_EN BIT(0)
46 #define RG_DSI_BG_CKEN BIT(1)
48 #define RG_DSI_BG_FAST_CHARGE BIT(4)
63 #define RG_DSI_MPPLL_PLL_EN BIT(0)
65 #define RG_DSI_MPPLL_TXDIV0 GENMASK(4, 3)
71 #define RG_DSI_MPPLL_MONVC_EN BIT(10)
72 #define RG_DSI_MPPLL_MONREF_EN BIT(11)
73 #define RG_DSI_MPPLL_VOD_EN BIT(12)
76 #define RG_DSI_MPPLL_SDM_FRA_EN BIT(0)
77 #define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1)
78 #define RG_DSI_MPPLL_SDM_SSC_EN BIT(2)
87 #define RG_DSI_MPPLL_SDM_PWR_ON BIT(0)
88 #define RG_DSI_MPPLL_SDM_ISO_EN BIT(1)
89 #define RG_DSI_MPPLL_SDM_PWR_ACK BIT(8)
92 #define SW_CTRL_EN BIT(0)
95 #define SW_LNTC_LPTX_PRE_OE BIT(0)
96 #define SW_LNTC_LPTX_OE BIT(1)
97 #define SW_LNTC_LPTX_P BIT(2)
98 #define SW_LNTC_LPTX_N BIT(3)
99 #define SW_LNTC_HSTX_PRE_OE BIT(4)
100 #define SW_LNTC_HSTX_OE BIT(5)
101 #define SW_LNTC_HSTX_ZEROCLK BIT(6)
102 #define SW_LNT0_LPTX_PRE_OE BIT(7)
103 #define SW_LNT0_LPTX_OE BIT(8)
104 #define SW_LNT0_LPTX_P BIT(9)
105 #define SW_LNT0_LPTX_N BIT(10)
106 #define SW_LNT0_HSTX_PRE_OE BIT(11)
107 #define SW_LNT0_HSTX_OE BIT(12)
108 #define SW_LNT0_LPRX_EN BIT(13)
109 #define SW_LNT1_LPTX_PRE_OE BIT(14)
110 #define SW_LNT1_LPTX_OE BIT(15)
111 #define SW_LNT1_LPTX_P BIT(16)
112 #define SW_LNT1_LPTX_N BIT(17)
113 #define SW_LNT1_HSTX_PRE_OE BIT(18)
114 #define SW_LNT1_HSTX_OE BIT(19)
115 #define SW_LNT2_LPTX_PRE_OE BIT(20)
116 #define SW_LNT2_LPTX_OE BIT(21)
117 #define SW_LNT2_LPTX_P BIT(22)
118 #define SW_LNT2_LPTX_N BIT(23)
119 #define SW_LNT2_HSTX_PRE_OE BIT(24)
120 #define SW_LNT2_HSTX_OE BIT(25)
125 void __iomem *base = mipi_tx->regs; in mtk_mipi_tx_pll_prepare()
129 dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate); in mtk_mipi_tx_pll_prepare()
131 if (mipi_tx->data_rate >= 500000000) { in mtk_mipi_tx_pll_prepare()
135 } else if (mipi_tx->data_rate >= 250000000) { in mtk_mipi_tx_pll_prepare()
139 } else if (mipi_tx->data_rate >= 125000000) { in mtk_mipi_tx_pll_prepare()
140 txdiv = 4; in mtk_mipi_tx_pll_prepare()
143 } else if (mipi_tx->data_rate > 62000000) { in mtk_mipi_tx_pll_prepare()
147 } else if (mipi_tx->data_rate >= 50000000) { in mtk_mipi_tx_pll_prepare()
152 return -EINVAL; in mtk_mipi_tx_pll_prepare()
158 FIELD_PREP(RG_DSI_V02_SEL, 4) | in mtk_mipi_tx_pll_prepare()
159 FIELD_PREP(RG_DSI_V032_SEL, 4) | in mtk_mipi_tx_pll_prepare()
160 FIELD_PREP(RG_DSI_V04_SEL, 4) | in mtk_mipi_tx_pll_prepare()
161 FIELD_PREP(RG_DSI_V072_SEL, 4) | in mtk_mipi_tx_pll_prepare()
162 FIELD_PREP(RG_DSI_V10_SEL, 4) | in mtk_mipi_tx_pll_prepare()
163 FIELD_PREP(RG_DSI_V12_SEL, 4) | in mtk_mipi_tx_pll_prepare()
190 * PCW bit 24~30 = integer part of pcw in mtk_mipi_tx_pll_prepare()
191 * PCW bit 0~23 = fractional part of pcw in mtk_mipi_tx_pll_prepare()
192 * pcw = data_Rate*4*txdiv/(Ref_clk*2); in mtk_mipi_tx_pll_prepare()
193 * Post DIV =4, so need data_Rate*4 in mtk_mipi_tx_pll_prepare()
196 pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24, 26000000); in mtk_mipi_tx_pll_prepare()
209 mipi_tx->driver_data->mppll_preserve); in mtk_mipi_tx_pll_prepare()
217 void __iomem *base = mipi_tx->regs; in mtk_mipi_tx_pll_unprepare()
219 dev_dbg(mipi_tx->dev, "unprepare\n"); in mtk_mipi_tx_pll_unprepare()
260 reg <= MIPITX_DSI_DATA_LANE3; reg += 4) in mtk_mipi_tx_power_on_signal()
261 mtk_phy_set_bits(mipi_tx->regs + reg, RG_DSI_LNTx_LDOOUT_EN); in mtk_mipi_tx_power_on_signal()
263 mtk_phy_clear_bits(mipi_tx->regs + MIPITX_DSI_TOP_CON, in mtk_mipi_tx_power_on_signal()
272 mtk_phy_set_bits(mipi_tx->regs + MIPITX_DSI_TOP_CON, in mtk_mipi_tx_power_off_signal()
276 reg <= MIPITX_DSI_DATA_LANE3; reg += 4) in mtk_mipi_tx_power_off_signal()
277 mtk_phy_clear_bits(mipi_tx->regs + reg, RG_DSI_LNTx_LDOOUT_EN); in mtk_mipi_tx_power_off_signal()