Home
last modified time | relevance | path

Searched refs:nvkm_wr32 (Results 1 – 25 of 190) sorted by relevance

12345678

/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dnv40.c105 nvkm_wr32(device, 0x400720, 0x00000000); in nv40_gr_chan_fini()
106 nvkm_wr32(device, 0x400784, inst); in nv40_gr_chan_fini()
189 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile()
190 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile()
191 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile()
192 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv40_gr_tile()
193 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv40_gr_tile()
194 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_gr_tile()
198 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv40_gr_tile()
199 nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile()
[all …]
Dnv20.c42 nvkm_wr32(device, 0x400784, inst >> 4); in nv20_gr_chan_fini()
43 nvkm_wr32(device, 0x400788, 0x00000002); in nv20_gr_chan_fini()
48 nvkm_wr32(device, 0x400144, 0x10000000); in nv20_gr_chan_fini()
159 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv20_gr_tile()
160 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv20_gr_tile()
161 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv20_gr_tile()
163 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); in nv20_gr_tile()
164 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit); in nv20_gr_tile()
165 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); in nv20_gr_tile()
166 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch); in nv20_gr_tile()
[all …]
Dnv30.c109 nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, in nv30_gr_init()
112 nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); in nv30_gr_init()
113 nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); in nv30_gr_init()
115 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); in nv30_gr_init()
116 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000); in nv30_gr_init()
117 nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0); in nv30_gr_init()
118 nvkm_wr32(device, 0x400890, 0x01b463ff); in nv30_gr_init()
119 nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf2de0475); in nv30_gr_init()
120 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000); in nv30_gr_init()
121 nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); in nv30_gr_init()
[all …]
Dnv50.c315 nvkm_wr32(device, addr + 0x10, mp10); in nv50_gr_mp_trap()
316 nvkm_wr32(device, addr + 0x14, 0); in nv50_gr_mp_trap()
387 nvkm_wr32(device, ustatus_addr, 0xc0000000); in nv50_gr_tp_trap()
418 nvkm_wr32(device, 0x400500, 0x00000000); in nv50_gr_trap_handler()
443 nvkm_wr32(device, 0x400808, 0); in nv50_gr_trap_handler()
444 nvkm_wr32(device, 0x4008e8, nvkm_rd32(device, 0x4008e8) & 3); in nv50_gr_trap_handler()
445 nvkm_wr32(device, 0x400848, 0); in nv50_gr_trap_handler()
468 nvkm_wr32(device, 0x40084c, 0); in nv50_gr_trap_handler()
477 nvkm_wr32(device, 0x400804, 0xc0000000); in nv50_gr_trap_handler()
478 nvkm_wr32(device, 0x400108, 0x001); in nv50_gr_trap_handler()
[all …]
Dnv44.c44 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
45 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
46 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
53 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
54 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
55 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
56 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv44_gr_tile()
57 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv44_gr_tile()
58 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv44_gr_tile()
61 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
[all …]
Dnv10.c417 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, addr); \
425 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, addr); \
427 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, state[__i]); \
464 nvkm_wr32(device, NV10_PGRAPH_XFMODE0, 0x10000000); in nv17_gr_mthd_lma_window()
465 nvkm_wr32(device, NV10_PGRAPH_XFMODE1, 0x00000000); in nv17_gr_mthd_lma_window()
466 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); in nv17_gr_mthd_lma_window()
468 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); in nv17_gr_mthd_lma_window()
470 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); in nv17_gr_mthd_lma_window()
472 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); in nv17_gr_mthd_lma_window()
474 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); in nv17_gr_mthd_lma_window()
[all …]
Dgf100.c53 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); in gf100_gr_zbc_clear_color()
54 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); in gf100_gr_zbc_clear_color()
55 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); in gf100_gr_zbc_clear_color()
56 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); in gf100_gr_zbc_clear_color()
58 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); in gf100_gr_zbc_clear_color()
59 nvkm_wr32(device, 0x405820, zbc); in gf100_gr_zbc_clear_color()
60 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ in gf100_gr_zbc_clear_color()
104 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); in gf100_gr_zbc_clear_depth()
105 nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); in gf100_gr_zbc_clear_depth()
106 nvkm_wr32(device, 0x405820, zbc); in gf100_gr_zbc_clear_depth()
[all …]
Dga102.c47 nvkm_wr32(device, 0x41bcec, color[0]); in ga102_gr_zbc_clear_color()
48 nvkm_wr32(device, 0x41bcf0, color[1]); in ga102_gr_zbc_clear_color()
49 nvkm_wr32(device, 0x41bcf4, color[2]); in ga102_gr_zbc_clear_color()
50 nvkm_wr32(device, 0x41bcf8, color[3]); in ga102_gr_zbc_clear_color()
66 nvkm_wr32(device, 0x41a610, 0x00000000); in ga102_gr_gpccs_reset()
68 nvkm_wr32(device, 0x41a610, 0x00000001); in ga102_gr_gpccs_reset()
85 nvkm_wr32(device, 0x409614, 0x00000010); in ga102_gr_fecs_reset()
86 nvkm_wr32(device, 0x41a614, 0x00000020); in ga102_gr_fecs_reset()
88 nvkm_wr32(device, 0x409614, 0x00000110); in ga102_gr_fecs_reset()
89 nvkm_wr32(device, 0x41a614, 0x00000a20); in ga102_gr_fecs_reset()
[all …]
Dtu102.c32 nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x006e0003); in tu102_gr_init_fecs_exceptions()
47 nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + tpc * 4), sm); in tu102_gr_init_fs()
68 nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data); in tu102_gr_init_zcull()
72 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in tu102_gr_init_zcull()
74 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | in tu102_gr_init_zcull()
76 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); in tu102_gr_init_zcull()
79 nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); in tu102_gr_init_zcull()
87 nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf8001fff); in tu102_gr_init_gpc_mmu()
88 nvkm_wr32(device, 0x418890, 0x00000000); in tu102_gr_init_gpc_mmu()
89 nvkm_wr32(device, 0x418894, 0x00000000); in tu102_gr_init_gpc_mmu()
[all …]
Dgk20a.c184 nvkm_wr32(device, 0x419e44, 0x1ffffe); in gk20a_gr_set_hww_esr_report_mask()
185 nvkm_wr32(device, 0x419e4c, 0x7f); in gk20a_gr_set_hww_esr_report_mask()
195 nvkm_wr32(device, 0x40802c, 0x1); in gk20a_gr_init()
220 nvkm_wr32(device, 0x400500, 0x00010001); in gk20a_gr_init()
223 nvkm_wr32(device, 0x400100, 0xffffffff); in gk20a_gr_init()
224 nvkm_wr32(device, 0x40013c, 0xffffffff); in gk20a_gr_init()
227 nvkm_wr32(device, 0x409c24, 0x000f0000); in gk20a_gr_init()
230 nvkm_wr32(device, 0x404000, 0xc0000000); in gk20a_gr_init()
231 nvkm_wr32(device, 0x404600, 0xc0000000); in gk20a_gr_init()
237 nvkm_wr32(device, 0x419d0c, 0x2); in gk20a_gr_init()
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dgt215.c60 nvkm_wr32(device, 0x10a580, 0x00000001); in gt215_pmu_send()
64 nvkm_wr32(device, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) + in gt215_pmu_send()
66 nvkm_wr32(device, 0x10a1c4, process); in gt215_pmu_send()
67 nvkm_wr32(device, 0x10a1c4, message); in gt215_pmu_send()
68 nvkm_wr32(device, 0x10a1c4, data0); in gt215_pmu_send()
69 nvkm_wr32(device, 0x10a1c4, data1); in gt215_pmu_send()
70 nvkm_wr32(device, 0x10a4a0, (addr + 1) & 0x0f); in gt215_pmu_send()
73 nvkm_wr32(device, 0x10a580, 0x00000000); in gt215_pmu_send()
100 nvkm_wr32(device, 0x10a580, 0x00000002); in gt215_pmu_recv()
104 nvkm_wr32(device, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) + in gt215_pmu_recv()
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dnv04.c53 nvkm_wr32(device, NV03_PFIFO_CACHES, 0); in nv04_chan_stop()
59 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0); in nv04_chan_stop()
75 nvkm_wr32(device, c->regp, 0x00000000); in nv04_chan_stop()
78 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, 0); in nv04_chan_stop()
79 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUT, 0); in nv04_chan_stop()
80 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask); in nv04_chan_stop()
81 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); in nv04_chan_stop()
82 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_chan_stop()
87 nvkm_wr32(device, NV03_PFIFO_CACHES, 1); in nv04_chan_stop()
221 nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000000); in nv04_fifo_pause()
[all …]
Dnv40.c157 nvkm_wr32(device, reg, inst); in nv40_ectx_bind()
190 nvkm_wr32(device, 0x002040, 0x000000ff); in nv40_fifo_init()
191 nvkm_wr32(device, 0x002044, 0x2101ffff); in nv40_fifo_init()
192 nvkm_wr32(device, 0x002058, 0x00000001); in nv40_fifo_init()
194 nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | in nv40_fifo_init()
197 nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); in nv40_fifo_init()
203 nvkm_wr32(device, 0x002230, 0x00000001); in nv40_fifo_init()
211 nvkm_wr32(device, 0x002220, 0x00030002); in nv40_fifo_init()
214 nvkm_wr32(device, 0x002230, 0x00000000); in nv40_fifo_init()
215 nvkm_wr32(device, 0x002220, ((fb->ram->size - 512 * 1024 + in nv40_fifo_init()
[all …]
Dnv17.c101 nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff); in nv17_fifo_init()
102 nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); in nv17_fifo_init()
104 nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | in nv17_fifo_init()
107 nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); in nv17_fifo_init()
108 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8 | in nv17_fifo_init()
111 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask); in nv17_fifo_init()
113 nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff); in nv17_fifo_init()
114 nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff); in nv17_fifo_init()
116 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); in nv17_fifo_init()
117 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv17_fifo_init()
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv50.c74 nvkm_wr32(device, 0x00b308, 0x00000100); in nv50_mpeg_intr()
84 nvkm_wr32(device, 0x00b100, stat); in nv50_mpeg_intr()
85 nvkm_wr32(device, 0x00b230, 0x00000001); in nv50_mpeg_intr()
94 nvkm_wr32(device, 0x00b32c, 0x00000000); in nv50_mpeg_init()
95 nvkm_wr32(device, 0x00b314, 0x00000100); in nv50_mpeg_init()
96 nvkm_wr32(device, 0x00b0e0, 0x0000001a); in nv50_mpeg_init()
98 nvkm_wr32(device, 0x00b220, 0x00000044); in nv50_mpeg_init()
99 nvkm_wr32(device, 0x00b300, 0x00801ec1); in nv50_mpeg_init()
100 nvkm_wr32(device, 0x00b390, 0x00000000); in nv50_mpeg_init()
101 nvkm_wr32(device, 0x00b394, 0x00000000); in nv50_mpeg_init()
[all …]
Dnv31.c118 nvkm_wr32(device, 0x00b008 + (i * 0x10), tile->pitch); in nv31_mpeg_tile()
119 nvkm_wr32(device, 0x00b004 + (i * 0x10), tile->limit); in nv31_mpeg_tile()
120 nvkm_wr32(device, 0x00b000 + (i * 0x10), tile->addr); in nv31_mpeg_tile()
146 nvkm_wr32(device, 0x00b334, base); in nv31_mpeg_mthd_dma()
147 nvkm_wr32(device, 0x00b324, size); in nv31_mpeg_mthd_dma()
153 nvkm_wr32(device, 0x00b360, base); in nv31_mpeg_mthd_dma()
154 nvkm_wr32(device, 0x00b364, size); in nv31_mpeg_mthd_dma()
160 nvkm_wr32(device, 0x00b370, base); in nv31_mpeg_mthd_dma()
161 nvkm_wr32(device, 0x00b374, size); in nv31_mpeg_mthd_dma()
210 nvkm_wr32(device, 0x00b100, stat); in nv31_mpeg_intr()
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dtu102.c127 nvkm_wr32(device, 0x640008, tmp); in tu102_disp_init()
133 nvkm_wr32(device, 0x640144 + (i * 0x08), tmp); in tu102_disp_init()
142 nvkm_wr32(device, 0x640048 + (id * 0x020), tmp); in tu102_disp_init()
147 nvkm_wr32(device, 0x640680 + (id * 0x20) + j, tmp); in tu102_disp_init()
164 nvkm_wr32(device, 0x640010 + (i * 0x04), tmp); in tu102_disp_init()
177 nvkm_wr32(device, 0x610010, 0x00000008 | tmp); in tu102_disp_init()
178 nvkm_wr32(device, 0x610014, disp->inst->addr >> 16); in tu102_disp_init()
181 nvkm_wr32(device, 0x611cf0, 0x00000187); /* MSK. */ in tu102_disp_init()
182 nvkm_wr32(device, 0x611db0, 0x00000187); /* EN. */ in tu102_disp_init()
185 nvkm_wr32(device, 0x611cec, disp->head.mask << 16 | in tu102_disp_init()
[all …]
Dgv100.c112 nvkm_wr32(device, 0x6f0108 + hoff, vsi.header); in gv100_sor_hdmi_infoframe_vsi()
113 nvkm_wr32(device, 0x6f010c + hoff, vsi.subpack0_low); in gv100_sor_hdmi_infoframe_vsi()
114 nvkm_wr32(device, 0x6f0110 + hoff, vsi.subpack0_high); in gv100_sor_hdmi_infoframe_vsi()
115 nvkm_wr32(device, 0x6f0114 + hoff, 0x00000000); in gv100_sor_hdmi_infoframe_vsi()
116 nvkm_wr32(device, 0x6f0118 + hoff, 0x00000000); in gv100_sor_hdmi_infoframe_vsi()
117 nvkm_wr32(device, 0x6f011c + hoff, 0x00000000); in gv100_sor_hdmi_infoframe_vsi()
118 nvkm_wr32(device, 0x6f0120 + hoff, 0x00000000); in gv100_sor_hdmi_infoframe_vsi()
119 nvkm_wr32(device, 0x6f0124 + hoff, 0x00000000); in gv100_sor_hdmi_infoframe_vsi()
136 nvkm_wr32(device, 0x6f0008 + hoff, avi.header); in gv100_sor_hdmi_infoframe_avi()
137 nvkm_wr32(device, 0x6f000c + hoff, avi.subpack0_low); in gv100_sor_hdmi_infoframe_avi()
[all …]
Dgp102.c42 nvkm_wr32(device, 0x611494 + (ctrl * 0x0010), chan->push); in gp102_disp_dmac_init()
43 nvkm_wr32(device, 0x611498 + (ctrl * 0x0010), 0x00010000); in gp102_disp_dmac_init()
44 nvkm_wr32(device, 0x61149c + (ctrl * 0x0010), 0x00000001); in gp102_disp_dmac_init()
46 nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), chan->suspend_put); in gp102_disp_dmac_init()
47 nvkm_wr32(device, 0x610490 + (ctrl * 0x0010), 0x00000013); in gp102_disp_dmac_init()
109 nvkm_wr32(device, 0x611494, chan->push); in gp102_disp_core_init()
110 nvkm_wr32(device, 0x611498, 0x00010000); in gp102_disp_core_init()
111 nvkm_wr32(device, 0x61149c, 0x00000001); in gp102_disp_core_init()
113 nvkm_wr32(device, 0x640000, chan->suspend_put); in gp102_disp_core_init()
114 nvkm_wr32(device, 0x610490, 0x01000013); in gp102_disp_core_init()
[all …]
Dgf119.c53 nvkm_wr32(device, 0x10ec00 + soff, (i << 8) | data[i]); in gf119_sor_hda_eld()
55 nvkm_wr32(device, 0x10ec00 + soff, (i << 8)); in gf119_sor_hda_eld()
142 nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift)); in gf119_sor_dp_drive()
143 nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift)); in gf119_sor_dp_drive()
144 nvkm_wr32(device, 0x61c130 + loff, data[2]); in gf119_sor_dp_drive()
147 nvkm_wr32(device, 0x61c13c + loff, data[3] | (pc << shift)); in gf119_sor_dp_drive()
222 nvkm_wr32(device, 0x616738 + hoff, vsi.header); in gf119_sor_hdmi_infoframe_vsi()
223 nvkm_wr32(device, 0x61673c + hoff, vsi.subpack0_low); in gf119_sor_hdmi_infoframe_vsi()
224 nvkm_wr32(device, 0x616740 + hoff, vsi.subpack0_high); in gf119_sor_hdmi_infoframe_vsi()
243 nvkm_wr32(device, 0x61671c + hoff, avi.header); in gf119_sor_hdmi_infoframe_avi()
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/
Dfalcon.c76 nvkm_wr32(device, base + 0x004, 0x00000040); in nvkm_falcon_intr()
83 nvkm_wr32(device, base + 0x004, 0x00000010); in nvkm_falcon_intr()
89 nvkm_wr32(device, base + 0x004, intr); in nvkm_falcon_intr()
113 nvkm_wr32(device, base + 0x014, 0xffffffff); in nvkm_falcon_fini()
183 nvkm_wr32(device, base + 0x004, 0x00000010); in nvkm_falcon_init()
187 nvkm_wr32(device, base + 0x014, 0xffffffff); in nvkm_falcon_init()
266 nvkm_wr32(device, base + 0x618, 0x04000000); in nvkm_falcon_init()
268 nvkm_wr32(device, base + 0x618, 0x00000114); in nvkm_falcon_init()
269 nvkm_wr32(device, base + 0x11c, 0); in nvkm_falcon_init()
270 nvkm_wr32(device, base + 0x110, addr >> 8); in nvkm_falcon_init()
[all …]
Dxtensa.c70 nvkm_wr32(device, base + 0xc20, intr); in nvkm_xtensa_intr()
85 nvkm_wr32(device, base + 0xd84, 0); /* INTR_EN */ in nvkm_xtensa_fini()
86 nvkm_wr32(device, base + 0xd94, 0); /* FIFO_CTRL */ in nvkm_xtensa_fini()
140 nvkm_wr32(device, base + 0xd10, 0x1fffffff); /* ?? */ in nvkm_xtensa_init()
141 nvkm_wr32(device, base + 0xd08, 0x0fffffff); /* ?? */ in nvkm_xtensa_init()
143 nvkm_wr32(device, base + 0xd28, xtensa->func->unkd28); /* ?? */ in nvkm_xtensa_init()
144 nvkm_wr32(device, base + 0xc20, 0x3f); /* INTR */ in nvkm_xtensa_init()
145 nvkm_wr32(device, base + 0xd84, 0x3f); /* INTR_EN */ in nvkm_xtensa_init()
147 nvkm_wr32(device, base + 0xcc0, addr >> 8); /* XT_REGION_BASE */ in nvkm_xtensa_init()
148 nvkm_wr32(device, base + 0xcc4, 0x1c); /* XT_REGION_SETUP */ in nvkm_xtensa_init()
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c159 nvkm_wr32(device, 0x001584, in setPLL_single()
166 nvkm_wr32(device, reg, pv->log2P << 16 | (oldpll & 0xffff)); in setPLL_single()
169 nvkm_wr32(device, reg, (oldpll & 0xffff0000) | pv->NM1); in setPLL_single()
178 nvkm_wr32(device, reg, pll); in setPLL_single()
181 nvkm_wr32(device, 0x001584, saved_powerctrl_1); in setPLL_single()
238 nvkm_wr32(device, 0x001584, in setPLL_double_highregs()
259 nvkm_wr32(device, 0xc040, savedc040 & ~(3 << shift_c040)); in setPLL_double_highregs()
263 nvkm_wr32(device, 0x680580, ramdac580); in setPLL_double_highregs()
266 nvkm_wr32(device, reg2, pll2); in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dg84.c64 nvkm_wr32(device, 0x20000, 0x000003ff); in g84_therm_program_alarms()
67 nvkm_wr32(device, 0x20484, sensor->thrs_shutdown.hysteresis); in g84_therm_program_alarms()
68 nvkm_wr32(device, 0x20480, sensor->thrs_shutdown.temp); in g84_therm_program_alarms()
71 nvkm_wr32(device, 0x204c4, sensor->thrs_fan_boost.temp); in g84_therm_program_alarms()
74 nvkm_wr32(device, 0x204c0, sensor->thrs_critical.temp); in g84_therm_program_alarms()
77 nvkm_wr32(device, 0x20414, sensor->thrs_down_clock.temp); in g84_therm_program_alarms()
110 nvkm_wr32(device, thrs_reg, thrs->temp - thrs->hysteresis); in g84_therm_threshold_hyst_emulation()
113 nvkm_wr32(device, thrs_reg, thrs->temp); in g84_therm_threshold_hyst_emulation()
187 nvkm_wr32(device, 0x20100, 0xffffffff); in g84_therm_intr()
188 nvkm_wr32(device, 0x1100, 0x10000); /* PBUS */ in g84_therm_intr()
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
Dnv44.c45 nvkm_wr32(device, 0x100850, 0x80000000); in nv44_mmu_init()
46 nvkm_wr32(device, 0x100818, mmu->vmm->null); in nv44_mmu_init()
47 nvkm_wr32(device, 0x100804, (nvkm_memory_size(pt) / 4) * 4096); in nv44_mmu_init()
48 nvkm_wr32(device, 0x100850, 0x00008000); in nv44_mmu_init()
50 nvkm_wr32(device, 0x100820, 0x00000000); in nv44_mmu_init()
51 nvkm_wr32(device, 0x10082c, 0x00000001); in nv44_mmu_init()
52 nvkm_wr32(device, 0x100800, addr | 0x00000010); in nv44_mmu_init()

12345678