53 	nvkm_wr32(device, NV03_PFIFO_CACHES, 0);  in nv04_chan_stop()
59 		nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0);  in nv04_chan_stop()
75 			nvkm_wr32(device, c->regp, 0x00000000);  in nv04_chan_stop()
78 		nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, 0);  in nv04_chan_stop()
79 		nvkm_wr32(device, NV03_PFIFO_CACHE1_PUT, 0);  in nv04_chan_stop()
80 		nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask);  in nv04_chan_stop()
81 		nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);  in nv04_chan_stop()
82 		nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);  in nv04_chan_stop()
87 	nvkm_wr32(device, NV03_PFIFO_CACHES, 1);  in nv04_chan_stop()
221 	nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000000);  in nv04_fifo_pause()
241 		nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);  in nv04_fifo_pause()
243 	nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0x00000000);  in nv04_fifo_pause()
254 	nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000001);  in nv04_fifo_start()
285 		nvkm_wr32(device, 0x003280, (engine &= ~mask));  in nv04_fifo_swmthd()
338 	nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0);  in nv04_fifo_intr_cache_error()
339 	nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);  in nv04_fifo_intr_cache_error()
341 	nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0,  in nv04_fifo_intr_cache_error()
343 	nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4);  in nv04_fifo_intr_cache_error()
344 	nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0,  in nv04_fifo_intr_cache_error()
346 	nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0);  in nv04_fifo_intr_cache_error()
348 	nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH,  in nv04_fifo_intr_cache_error()
350 	nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);  in nv04_fifo_intr_cache_error()
382 		nvkm_wr32(device, 0x003364, 0x00000000);  in nv04_fifo_intr_dma_pusher()
384 			nvkm_wr32(device, 0x003244, dma_put);  in nv04_fifo_intr_dma_pusher()
385 			nvkm_wr32(device, 0x003328, ho_put);  in nv04_fifo_intr_dma_pusher()
388 			nvkm_wr32(device, 0x003334, ib_put);  in nv04_fifo_intr_dma_pusher()
396 			nvkm_wr32(device, 0x003244, dma_put);  in nv04_fifo_intr_dma_pusher()
400 	nvkm_wr32(device, 0x003228, 0x00000000);  in nv04_fifo_intr_dma_pusher()
401 	nvkm_wr32(device, 0x003220, 0x00000001);  in nv04_fifo_intr_dma_pusher()
402 	nvkm_wr32(device, 0x002100, NV_PFIFO_INTR_DMA_PUSHER);  in nv04_fifo_intr_dma_pusher()
416 	nvkm_wr32(device, NV03_PFIFO_CACHES, 0);  in nv04_fifo_intr()
433 		nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_SEMAPHORE);  in nv04_fifo_intr()
436 		nvkm_wr32(device, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);  in nv04_fifo_intr()
438 		nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4);  in nv04_fifo_intr()
439 		nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);  in nv04_fifo_intr()
445 			nvkm_wr32(device, 0x002100, 0x00000010);  in nv04_fifo_intr()
449 			nvkm_wr32(device, 0x002100, 0x40000000);  in nv04_fifo_intr()
458 		nvkm_wr32(device, NV03_PFIFO_INTR_0, stat);  in nv04_fifo_intr()
461 	nvkm_wr32(device, NV03_PFIFO_CACHES, reassign);  in nv04_fifo_intr()
474 	nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff);  in nv04_fifo_init()
475 	nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);  in nv04_fifo_init()
477 	nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |  in nv04_fifo_init()
480 	nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8);  in nv04_fifo_init()
481 	nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8);  in nv04_fifo_init()
483 	nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask);  in nv04_fifo_init()
485 	nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff);  in nv04_fifo_init()
486 	nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff);  in nv04_fifo_init()
488 	nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);  in nv04_fifo_init()
489 	nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);  in nv04_fifo_init()
490 	nvkm_wr32(device, NV03_PFIFO_CACHES, 1);  in nv04_fifo_init()