Lines Matching refs:nvkm_wr32
105 nvkm_wr32(device, 0x400720, 0x00000000); in nv40_gr_chan_fini()
106 nvkm_wr32(device, 0x400784, inst); in nv40_gr_chan_fini()
189 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile()
190 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile()
191 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile()
192 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv40_gr_tile()
193 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv40_gr_tile()
194 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_gr_tile()
198 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv40_gr_tile()
199 nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile()
204 nvkm_wr32(device, NV41_PGRAPH_ZCOMP0(i), tile->zcomp); in nv40_gr_tile()
205 nvkm_wr32(device, NV41_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile()
214 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile()
215 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile()
216 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile()
217 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv40_gr_tile()
218 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv40_gr_tile()
219 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_gr_tile()
220 nvkm_wr32(device, NV47_PGRAPH_ZCOMP0(i), tile->zcomp); in nv40_gr_tile()
221 nvkm_wr32(device, NV47_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile()
267 nvkm_wr32(device, NV03_PGRAPH_INTR, stat); in nv40_gr_intr()
268 nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001); in nv40_gr_intr()
300 nvkm_wr32(device, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); in nv40_gr_init()
302 nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); in nv40_gr_init()
303 nvkm_wr32(device, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF); in nv40_gr_init()
305 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); in nv40_gr_init()
306 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000); in nv40_gr_init()
307 nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0); in nv40_gr_init()
308 nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xe0de8055); in nv40_gr_init()
309 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000); in nv40_gr_init()
310 nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f); in nv40_gr_init()
312 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10010100); in nv40_gr_init()
313 nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF); in nv40_gr_init()
319 nvkm_wr32(device, 0x405000, i); in nv40_gr_init()
323 nvkm_wr32(device, 0x4009b0, 0x83280fff); in nv40_gr_init()
324 nvkm_wr32(device, 0x4009b4, 0x000000a0); in nv40_gr_init()
326 nvkm_wr32(device, 0x400820, 0x83280eff); in nv40_gr_init()
327 nvkm_wr32(device, 0x400824, 0x000000a0); in nv40_gr_init()
333 nvkm_wr32(device, 0x4009b8, 0x0078e366); in nv40_gr_init()
334 nvkm_wr32(device, 0x4009bc, 0x0000014c); in nv40_gr_init()
339 nvkm_wr32(device, 0x400828, 0x007596ff); in nv40_gr_init()
340 nvkm_wr32(device, 0x40082c, 0x00000108); in nv40_gr_init()
343 nvkm_wr32(device, 0x400828, 0x0072cb77); in nv40_gr_init()
344 nvkm_wr32(device, 0x40082c, 0x00000108); in nv40_gr_init()
351 nvkm_wr32(device, 0x400860, 0); in nv40_gr_init()
352 nvkm_wr32(device, 0x400864, 0); in nv40_gr_init()
357 nvkm_wr32(device, 0x400828, 0x07830610); in nv40_gr_init()
358 nvkm_wr32(device, 0x40082c, 0x0000016A); in nv40_gr_init()
364 nvkm_wr32(device, 0x400b38, 0x2ffff800); in nv40_gr_init()
365 nvkm_wr32(device, 0x400b3c, 0x00006000); in nv40_gr_init()
371 nvkm_wr32(device, 0x400bc4, 0x1003d888); in nv40_gr_init()
372 nvkm_wr32(device, 0x400bbc, 0xb7a7b500); in nv40_gr_init()
375 nvkm_wr32(device, 0x400bc4, 0x0000e024); in nv40_gr_init()
376 nvkm_wr32(device, 0x400bbc, 0xb7a7b520); in nv40_gr_init()
381 nvkm_wr32(device, 0x400bc4, 0x1003d888); in nv40_gr_init()
382 nvkm_wr32(device, 0x400bbc, 0xb7a7b540); in nv40_gr_init()
392 nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); in nv40_gr_init()
393 nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); in nv40_gr_init()
394 nvkm_wr32(device, 0x4069A4, nvkm_rd32(device, 0x100200)); in nv40_gr_init()
395 nvkm_wr32(device, 0x4069A8, nvkm_rd32(device, 0x100204)); in nv40_gr_init()
396 nvkm_wr32(device, 0x400820, 0); in nv40_gr_init()
397 nvkm_wr32(device, 0x400824, 0); in nv40_gr_init()
398 nvkm_wr32(device, 0x400864, vramsz); in nv40_gr_init()
399 nvkm_wr32(device, 0x400868, vramsz); in nv40_gr_init()
410 nvkm_wr32(device, 0x4009F0, nvkm_rd32(device, 0x100200)); in nv40_gr_init()
411 nvkm_wr32(device, 0x4009F4, nvkm_rd32(device, 0x100204)); in nv40_gr_init()
414 nvkm_wr32(device, 0x400DF0, nvkm_rd32(device, 0x100200)); in nv40_gr_init()
415 nvkm_wr32(device, 0x400DF4, nvkm_rd32(device, 0x100204)); in nv40_gr_init()
418 nvkm_wr32(device, 0x4069F0, nvkm_rd32(device, 0x100200)); in nv40_gr_init()
419 nvkm_wr32(device, 0x4069F4, nvkm_rd32(device, 0x100204)); in nv40_gr_init()
420 nvkm_wr32(device, 0x400840, 0); in nv40_gr_init()
421 nvkm_wr32(device, 0x400844, 0); in nv40_gr_init()
422 nvkm_wr32(device, 0x4008A0, vramsz); in nv40_gr_init()
423 nvkm_wr32(device, 0x4008A4, vramsz); in nv40_gr_init()