70 	nvkm_wr32(device, base + 0xc20, intr);  in nvkm_xtensa_intr()
85 	nvkm_wr32(device, base + 0xd84, 0); /* INTR_EN */  in nvkm_xtensa_fini()
86 	nvkm_wr32(device, base + 0xd94, 0); /* FIFO_CTRL */  in nvkm_xtensa_fini()
140 	nvkm_wr32(device, base + 0xd10, 0x1fffffff); /* ?? */  in nvkm_xtensa_init()
141 	nvkm_wr32(device, base + 0xd08, 0x0fffffff); /* ?? */  in nvkm_xtensa_init()
143 	nvkm_wr32(device, base + 0xd28, xtensa->func->unkd28); /* ?? */  in nvkm_xtensa_init()
144 	nvkm_wr32(device, base + 0xc20, 0x3f); /* INTR */  in nvkm_xtensa_init()
145 	nvkm_wr32(device, base + 0xd84, 0x3f); /* INTR_EN */  in nvkm_xtensa_init()
147 	nvkm_wr32(device, base + 0xcc0, addr >> 8); /* XT_REGION_BASE */  in nvkm_xtensa_init()
148 	nvkm_wr32(device, base + 0xcc4, 0x1c); /* XT_REGION_SETUP */  in nvkm_xtensa_init()
149 	nvkm_wr32(device, base + 0xcc8, size >> 8); /* XT_REGION_LIMIT */  in nvkm_xtensa_init()
152 	nvkm_wr32(device, base + 0xde0, tmp); /* SCRATCH_H2X */  in nvkm_xtensa_init()
154 	nvkm_wr32(device, base + 0xce8, 0xf); /* XT_REGION_SETUP */  in nvkm_xtensa_init()
156 	nvkm_wr32(device, base + 0xc20, 0x3f); /* INTR */  in nvkm_xtensa_init()
157 	nvkm_wr32(device, base + 0xd84, 0x3f); /* INTR_EN */  in nvkm_xtensa_init()