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Searched refs:reg_num (Results 1 – 25 of 163) sorted by relevance

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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn201/
Dirq_service_dcn201.c152 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
153 .enable_reg = SRI(reg1, block, reg_num),\
155 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
157 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
158 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
160 .ack_reg = SRI(reg2, block, reg_num),\
162 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
164 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
166 #define hpd_int_entry(reg_num)\ argument
167 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dce120/
Dirq_service_dce120.c103 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
104 .enable_reg = SRI(reg1, block, reg_num),\
106 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
108 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
109 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
111 .ack_reg = SRI(reg2, block, reg_num),\
113 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
115 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
117 #define hpd_int_entry(reg_num)\ argument
118 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn303/
Dirq_service_dcn303.c138 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
139 .enable_reg = SRI(reg1, block, reg_num),\
140 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
142 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
143 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
145 .ack_reg = SRI(reg2, block, reg_num),\
146 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
147 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
151 #define hpd_int_entry(reg_num)\ argument
152 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dce80/
Dirq_service_dce80.c92 #define hpd_int_entry(reg_num)\ argument
93 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
94 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
100 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
103 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
107 #define hpd_rx_int_entry(reg_num)\ argument
108 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
109 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
114 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
117 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn35/
Dirq_service_dcn35.c207 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
208 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
209 REG_STRUCT[base + reg_num].enable_mask = \
210 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
211 REG_STRUCT[base + reg_num].enable_value[0] = \
212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
213 REG_STRUCT[base + reg_num].enable_value[1] = \
214 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
215 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
216 REG_STRUCT[base + reg_num].ack_mask = \
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn351/
Dirq_service_dcn351.c186 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
187 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
188 REG_STRUCT[base + reg_num].enable_mask = \
189 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
190 REG_STRUCT[base + reg_num].enable_value[0] = \
191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
192 REG_STRUCT[base + reg_num].enable_value[1] = \
193 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
194 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
195 REG_STRUCT[base + reg_num].ack_mask = \
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn20/
Dirq_service_dcn20.c203 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
204 .enable_reg = SRI(reg1, block, reg_num),\
206 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
208 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
209 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
211 .ack_reg = SRI(reg2, block, reg_num),\
213 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
215 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
219 #define hpd_int_entry(reg_num)\ argument
220 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn10/
Dirq_service_dcn10.c200 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
201 .enable_reg = SRI(reg1, block, reg_num),\
203 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
205 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
206 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
208 .ack_reg = SRI(reg2, block, reg_num),\
210 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
212 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
214 #define hpd_int_entry(reg_num)\ argument
215 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/linux-6.12.1/arch/sparc/kernel/
Dpcr.c55 static u64 direct_pcr_read(unsigned long reg_num) in direct_pcr_read() argument
59 WARN_ON_ONCE(reg_num != 0); in direct_pcr_read()
64 static void direct_pcr_write(unsigned long reg_num, u64 val) in direct_pcr_write() argument
66 WARN_ON_ONCE(reg_num != 0); in direct_pcr_write()
70 static u64 direct_pic_read(unsigned long reg_num) in direct_pic_read() argument
74 WARN_ON_ONCE(reg_num != 0); in direct_pic_read()
79 static void direct_pic_write(unsigned long reg_num, u64 val) in direct_pic_write() argument
81 WARN_ON_ONCE(reg_num != 0); in direct_pic_write()
111 static void n2_pcr_write(unsigned long reg_num, u64 val) in n2_pcr_write() argument
115 WARN_ON_ONCE(reg_num != 0); in n2_pcr_write()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dce60/
Dirq_service_dce60.c101 #define hpd_int_entry(reg_num)\ argument
102 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
103 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
109 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
112 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
116 #define hpd_rx_int_entry(reg_num)\ argument
117 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
118 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
123 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
126 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn32/
Dirq_service_dcn32.c209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
210 .enable_reg = SRI(reg1, block, reg_num),\
212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
217 .ack_reg = SRI(reg2, block, reg_num),\
219 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
221 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
237 #define hpd_int_entry(reg_num)\ argument
238 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn315/
Dirq_service_dcn315.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
216 .enable_reg = SRI(reg1, block, reg_num),\
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
220 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
221 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
223 .ack_reg = SRI(reg2, block, reg_num),\
225 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
227 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
243 #define hpd_int_entry(reg_num)\ argument
244 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn302/
Dirq_service_dcn302.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
196 .enable_reg = SRI(reg1, block, reg_num),\
197 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
200 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
202 .ack_reg = SRI(reg2, block, reg_num),\
203 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
204 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
227 #define hpd_int_entry(reg_num)\ argument
228 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn401/
Dirq_service_dcn401.c189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
190 .enable_reg = SRI(reg1, block, reg_num),\
192 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
195 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
197 .ack_reg = SRI(reg2, block, reg_num),\
199 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
217 #define hpd_int_entry(reg_num)\ argument
218 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn314/
Dirq_service_dcn314.c210 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
211 .enable_reg = SRI(reg1, block, reg_num),\
213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
216 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
218 .ack_reg = SRI(reg2, block, reg_num),\
220 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
222 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
238 #define hpd_int_entry(reg_num)\ argument
239 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn30/
Dirq_service_dcn30.c220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
221 .enable_reg = SRI(reg1, block, reg_num),\
223 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
225 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
226 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
228 .ack_reg = SRI(reg2, block, reg_num),\
230 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
232 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
248 #define hpd_int_entry(reg_num)\ argument
249 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn31/
Dirq_service_dcn31.c208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
209 .enable_reg = SRI(reg1, block, reg_num),\
211 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
216 .ack_reg = SRI(reg2, block, reg_num),\
218 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
220 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
236 #define hpd_int_entry(reg_num)\ argument
237 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dcn21/
Dirq_service_dcn21.c213 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
214 .enable_reg = SRI(reg1, block, reg_num),\
216 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
219 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
221 .ack_reg = SRI(reg2, block, reg_num),\
223 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
225 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
241 #define hpd_int_entry(reg_num)\ argument
242 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/irq/dce110/
Dirq_service_dce110.c89 #define hpd_int_entry(reg_num)\ argument
90 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
91 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
97 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
100 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
104 #define hpd_rx_int_entry(reg_num)\ argument
105 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
106 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
111 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
114 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
[all …]
/linux-6.12.1/arch/riscv/kvm/
Dvcpu_onereg.c208 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_config() local
216 switch (reg_num) { in kvm_riscv_vcpu_get_reg_config()
257 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_config() local
268 switch (reg_num) { in kvm_riscv_vcpu_set_reg_config()
362 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_core() local
369 if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long)) in kvm_riscv_vcpu_get_reg_core()
372 if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc)) in kvm_riscv_vcpu_get_reg_core()
374 else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num && in kvm_riscv_vcpu_get_reg_core()
375 reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6)) in kvm_riscv_vcpu_get_reg_core()
376 reg_val = ((unsigned long *)cntx)[reg_num]; in kvm_riscv_vcpu_get_reg_core()
[all …]
Dvcpu_fp.c84 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_fp() local
93 if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr)) in kvm_riscv_vcpu_get_reg_fp()
95 else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <= reg_num) && in kvm_riscv_vcpu_get_reg_fp()
96 reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) in kvm_riscv_vcpu_get_reg_fp()
97 reg_val = &cntx->fp.f.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp()
102 if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) { in kvm_riscv_vcpu_get_reg_fp()
106 } else if ((KVM_REG_RISCV_FP_D_REG(f[0]) <= reg_num) && in kvm_riscv_vcpu_get_reg_fp()
107 reg_num <= KVM_REG_RISCV_FP_D_REG(f[31])) { in kvm_riscv_vcpu_get_reg_fp()
110 reg_val = &cntx->fp.d.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp()
129 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_fp() local
[all …]
Dvcpu_sbi.c175 unsigned long reg_num, in riscv_vcpu_set_sbi_ext_single() argument
184 sext = riscv_vcpu_get_sbi_ext(vcpu, reg_num); in riscv_vcpu_set_sbi_ext_single()
196 unsigned long reg_num, in riscv_vcpu_get_sbi_ext_single() argument
202 sext = riscv_vcpu_get_sbi_ext(vcpu, reg_num); in riscv_vcpu_get_sbi_ext_single()
213 unsigned long reg_num, in riscv_vcpu_set_sbi_ext_multi() argument
218 if (reg_num > KVM_REG_RISCV_SBI_MULTI_REG_LAST) in riscv_vcpu_set_sbi_ext_multi()
222 ext_id = i + reg_num * BITS_PER_LONG; in riscv_vcpu_set_sbi_ext_multi()
233 unsigned long reg_num, in riscv_vcpu_get_sbi_ext_multi() argument
238 if (reg_num > KVM_REG_RISCV_SBI_MULTI_REG_LAST) in riscv_vcpu_get_sbi_ext_multi()
242 ext_id = i + reg_num * BITS_PER_LONG; in riscv_vcpu_get_sbi_ext_multi()
[all …]
Dvcpu_vector.c96 unsigned long reg_num, in kvm_riscv_vcpu_vreg_addr() argument
103 if (reg_num < KVM_REG_RISCV_VECTOR_REG(0)) { in kvm_riscv_vcpu_vreg_addr()
106 switch (reg_num) { in kvm_riscv_vcpu_vreg_addr()
126 } else if (reg_num <= KVM_REG_RISCV_VECTOR_REG(31)) { in kvm_riscv_vcpu_vreg_addr()
130 (reg_num - KVM_REG_RISCV_VECTOR_REG(0)) * vlenb; in kvm_riscv_vcpu_vreg_addr()
144 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_vector() local
154 rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, &reg_addr); in kvm_riscv_vcpu_get_reg_vector()
170 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_vector() local
180 if (reg_num == KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)) { in kvm_riscv_vcpu_set_reg_vector()
192 rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, &reg_addr); in kvm_riscv_vcpu_set_reg_vector()
/linux-6.12.1/drivers/video/fbdev/via/
Dhw.h355 int reg_num; member
361 int reg_num; member
367 int reg_num; member
373 int reg_num; member
379 int reg_num; member
385 int reg_num; member
391 int reg_num; member
397 int reg_num; member
403 int reg_num; member
409 int reg_num; member
[all …]
/linux-6.12.1/drivers/irqchip/
Dirq-imx-irqsteer.c35 int reg_num; member
45 return (data->reg_num - irqnum / 32 - 1); in imx_irqsteer_get_reg_index()
56 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_unmask()
58 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_unmask()
70 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_mask()
72 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_mask()
146 if (hwirq >= data->reg_num * 32) in imx_irqsteer_irq_handler()
150 CHANSTATUS(idx, data->reg_num)); in imx_irqsteer_irq_handler()
196 data->reg_num = irqs_num / 32; in imx_irqsteer_probe()
200 sizeof(u32) * data->reg_num, in imx_irqsteer_probe()
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