1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "include/logger_interface.h"
28 #include "../dce110/irq_service_dce110.h"
29
30 #include "dcn/dcn_3_5_0_offset.h"
31 #include "dcn/dcn_3_5_0_sh_mask.h"
32
33 #include "irq_service_dcn35.h"
34
35 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
36
to_dal_irq_source_dcn35(struct irq_service * irq_service,uint32_t src_id,uint32_t ext_id)37 static enum dc_irq_source to_dal_irq_source_dcn35(
38 struct irq_service *irq_service,
39 uint32_t src_id,
40 uint32_t ext_id)
41 {
42 switch (src_id) {
43 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
44 return DC_IRQ_SOURCE_VBLANK1;
45 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
46 return DC_IRQ_SOURCE_VBLANK2;
47 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
48 return DC_IRQ_SOURCE_VBLANK3;
49 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
50 return DC_IRQ_SOURCE_VBLANK4;
51 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
52 return DC_IRQ_SOURCE_VBLANK5;
53 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
54 return DC_IRQ_SOURCE_VBLANK6;
55 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
56 return DC_IRQ_SOURCE_DC1_VLINE0;
57 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
58 return DC_IRQ_SOURCE_DC2_VLINE0;
59 case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
60 return DC_IRQ_SOURCE_DC3_VLINE0;
61 case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
62 return DC_IRQ_SOURCE_DC4_VLINE0;
63 case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
64 return DC_IRQ_SOURCE_DC5_VLINE0;
65 case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
66 return DC_IRQ_SOURCE_DC6_VLINE0;
67 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
68 return DC_IRQ_SOURCE_PFLIP1;
69 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
70 return DC_IRQ_SOURCE_PFLIP2;
71 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
72 return DC_IRQ_SOURCE_PFLIP3;
73 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
74 return DC_IRQ_SOURCE_PFLIP4;
75 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
76 return DC_IRQ_SOURCE_PFLIP5;
77 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
78 return DC_IRQ_SOURCE_PFLIP6;
79 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
80 return DC_IRQ_SOURCE_VUPDATE1;
81 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
82 return DC_IRQ_SOURCE_VUPDATE2;
83 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
84 return DC_IRQ_SOURCE_VUPDATE3;
85 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
86 return DC_IRQ_SOURCE_VUPDATE4;
87 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
88 return DC_IRQ_SOURCE_VUPDATE5;
89 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
90 return DC_IRQ_SOURCE_VUPDATE6;
91 case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
92 return DC_IRQ_SOURCE_DMCUB_OUTBOX;
93 case DCN_1_0__SRCID__DC_HPD1_INT:
94 /* generic src_id for all HPD and HPDRX interrupts */
95 switch (ext_id) {
96 case DCN_1_0__CTXID__DC_HPD1_INT:
97 return DC_IRQ_SOURCE_HPD1;
98 case DCN_1_0__CTXID__DC_HPD2_INT:
99 return DC_IRQ_SOURCE_HPD2;
100 case DCN_1_0__CTXID__DC_HPD3_INT:
101 return DC_IRQ_SOURCE_HPD3;
102 case DCN_1_0__CTXID__DC_HPD4_INT:
103 return DC_IRQ_SOURCE_HPD4;
104 case DCN_1_0__CTXID__DC_HPD5_INT:
105 return DC_IRQ_SOURCE_HPD5;
106 case DCN_1_0__CTXID__DC_HPD6_INT:
107 return DC_IRQ_SOURCE_HPD6;
108 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
109 return DC_IRQ_SOURCE_HPD1RX;
110 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
111 return DC_IRQ_SOURCE_HPD2RX;
112 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
113 return DC_IRQ_SOURCE_HPD3RX;
114 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
115 return DC_IRQ_SOURCE_HPD4RX;
116 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
117 return DC_IRQ_SOURCE_HPD5RX;
118 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
119 return DC_IRQ_SOURCE_HPD6RX;
120 default:
121 return DC_IRQ_SOURCE_INVALID;
122 }
123 break;
124
125 default:
126 return DC_IRQ_SOURCE_INVALID;
127 }
128 }
129
hpd_ack(struct irq_service * irq_service,const struct irq_source_info * info)130 static bool hpd_ack(
131 struct irq_service *irq_service,
132 const struct irq_source_info *info)
133 {
134 uint32_t addr = info->status_reg;
135 uint32_t value = dm_read_reg(irq_service->ctx, addr);
136 uint32_t current_status =
137 get_reg_field_value(
138 value,
139 HPD0_DC_HPD_INT_STATUS,
140 DC_HPD_SENSE_DELAYED);
141
142 dal_irq_service_ack_generic(irq_service, info);
143
144 value = dm_read_reg(irq_service->ctx, info->enable_reg);
145
146 set_reg_field_value(
147 value,
148 current_status ? 0 : 1,
149 HPD0_DC_HPD_INT_CONTROL,
150 DC_HPD_INT_POLARITY);
151
152 dm_write_reg(irq_service->ctx, info->enable_reg, value);
153
154 return true;
155 }
156
157 static struct irq_source_info_funcs hpd_irq_info_funcs = {
158 .set = NULL,
159 .ack = hpd_ack
160 };
161
162 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
163 .set = NULL,
164 .ack = NULL
165 };
166
167 static struct irq_source_info_funcs pflip_irq_info_funcs = {
168 .set = NULL,
169 .ack = NULL
170 };
171
172 static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
173 .set = NULL,
174 .ack = NULL
175 };
176
177 static struct irq_source_info_funcs vblank_irq_info_funcs = {
178 .set = NULL,
179 .ack = NULL
180 };
181
182 static struct irq_source_info_funcs outbox_irq_info_funcs = {
183 .set = NULL,
184 .ack = NULL
185 };
186
187 static struct irq_source_info_funcs vline0_irq_info_funcs = {
188 .set = NULL,
189 .ack = NULL
190 };
191
192 #undef BASE_INNER
193 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
194
195 /* compile time expand base address. */
196 #define BASE(seg) \
197 BASE_INNER(seg)
198
199 #define SRI(reg_name, block, id)\
200 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
201 reg ## block ## id ## _ ## reg_name
202
203 #define SRI_DMUB(reg_name)\
204 BASE(reg ## reg_name ## _BASE_IDX) + \
205 reg ## reg_name
206
207 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\
208 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
209 REG_STRUCT[base + reg_num].enable_mask = \
210 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
211 REG_STRUCT[base + reg_num].enable_value[0] = \
212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
213 REG_STRUCT[base + reg_num].enable_value[1] = \
214 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
215 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
216 REG_STRUCT[base + reg_num].ack_mask = \
217 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
218 REG_STRUCT[base + reg_num].ack_value = \
219 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
220
221 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\
222 REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\
223 REG_STRUCT[base].enable_mask = \
224 reg1 ## __ ## mask1 ## _MASK,\
225 REG_STRUCT[base].enable_value[0] = \
226 reg1 ## __ ## mask1 ## _MASK,\
227 REG_STRUCT[base].enable_value[1] = \
228 ~reg1 ## __ ## mask1 ## _MASK, \
229 REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
230 REG_STRUCT[base].ack_mask = \
231 reg2 ## __ ## mask2 ## _MASK,\
232 REG_STRUCT[base].ack_value = \
233 reg2 ## __ ## mask2 ## _MASK \
234
235 #define hpd_int_entry(reg_num)\
236 IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1, HPD, reg_num,\
237 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
238 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
239 REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\
240 REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
241
242 #define hpd_rx_int_entry(reg_num)\
243 IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1RX, HPD, reg_num,\
244 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
245 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
246 REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
247 REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\
248
249 #define pflip_int_entry(reg_num)\
250 IRQ_REG_ENTRY(DC_IRQ_SOURCE_PFLIP1, HUBPREQ, reg_num,\
251 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
252 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
253 REG_STRUCT[DC_IRQ_SOURCE_PFLIP1 + reg_num].funcs = &pflip_irq_info_funcs\
254
255 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
256 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
257 */
258 #define vupdate_no_lock_int_entry(reg_num)\
259 IRQ_REG_ENTRY(DC_IRQ_SOURCE_VUPDATE1, OTG, reg_num,\
260 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
261 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
262 REG_STRUCT[DC_IRQ_SOURCE_VUPDATE1 + reg_num].funcs = &vupdate_no_lock_irq_info_funcs\
263
264 #define vblank_int_entry(reg_num)\
265 IRQ_REG_ENTRY(DC_IRQ_SOURCE_VBLANK1, OTG, reg_num,\
266 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
267 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
268 REG_STRUCT[DC_IRQ_SOURCE_VBLANK1 + reg_num].funcs = &vblank_irq_info_funcs\
269
270 #define vline0_int_entry(reg_num)\
271 IRQ_REG_ENTRY(DC_IRQ_SOURCE_DC1_VLINE0, OTG, reg_num,\
272 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
273 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
274 REG_STRUCT[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num].funcs = &vline0_irq_info_funcs\
275
276 #define dmub_outbox_int_entry()\
277 IRQ_REG_ENTRY_DMUB(DC_IRQ_SOURCE_DMCUB_OUTBOX, \
278 DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
279 DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
280 REG_STRUCT[DC_IRQ_SOURCE_DMCUB_OUTBOX].funcs = &outbox_irq_info_funcs
281
282 #define dummy_irq_entry(irqno) \
283 REG_STRUCT[irqno].funcs = &dummy_irq_info_funcs\
284
285 #define i2c_int_entry(reg_num) \
286 dummy_irq_entry(DC_IRQ_SOURCE_I2C_DDC ## reg_num)
287
288 #define dp_sink_int_entry(reg_num) \
289 dummy_irq_entry(DC_IRQ_SOURCE_DPSINK ## reg_num)
290
291 #define gpio_pad_int_entry(reg_num) \
292 dummy_irq_entry(DC_IRQ_SOURCE_GPIOPAD ## reg_num)
293
294 #define dc_underflow_int_entry(reg_num) \
295 dummy_irq_entry(DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW)
296
297 static struct irq_source_info_funcs dummy_irq_info_funcs = {
298 .set = dal_irq_service_dummy_set,
299 .ack = dal_irq_service_dummy_ack
300 };
301
302 #define dcn35_irq_init_part_1() \
303 dummy_irq_entry(DC_IRQ_SOURCE_INVALID); \
304 hpd_int_entry(0); \
305 hpd_int_entry(1); \
306 hpd_int_entry(2); \
307 hpd_int_entry(3); \
308 hpd_int_entry(4); \
309 hpd_rx_int_entry(0); \
310 hpd_rx_int_entry(1); \
311 hpd_rx_int_entry(2); \
312 hpd_rx_int_entry(3); \
313 hpd_rx_int_entry(4); \
314 i2c_int_entry(1); \
315 i2c_int_entry(2); \
316 i2c_int_entry(3); \
317 i2c_int_entry(4); \
318 i2c_int_entry(5); \
319 i2c_int_entry(6); \
320 dp_sink_int_entry(1); \
321 dp_sink_int_entry(2); \
322 dp_sink_int_entry(3); \
323 dp_sink_int_entry(4); \
324 dp_sink_int_entry(5); \
325 dp_sink_int_entry(6); \
326 dummy_irq_entry(DC_IRQ_SOURCE_TIMER); \
327 pflip_int_entry(0); \
328 pflip_int_entry(1); \
329 pflip_int_entry(2); \
330 pflip_int_entry(3); \
331 dummy_irq_entry(DC_IRQ_SOURCE_PFLIP5); \
332 dummy_irq_entry(DC_IRQ_SOURCE_PFLIP6); \
333 dummy_irq_entry(DC_IRQ_SOURCE_PFLIP_UNDERLAY0); \
334 gpio_pad_int_entry(0); \
335 gpio_pad_int_entry(1); \
336 gpio_pad_int_entry(2); \
337 gpio_pad_int_entry(3); \
338 gpio_pad_int_entry(4); \
339 gpio_pad_int_entry(5); \
340 gpio_pad_int_entry(6); \
341 gpio_pad_int_entry(7); \
342 gpio_pad_int_entry(8); \
343 gpio_pad_int_entry(9); \
344 gpio_pad_int_entry(10); \
345 gpio_pad_int_entry(11); \
346 gpio_pad_int_entry(12); \
347 gpio_pad_int_entry(13); \
348 gpio_pad_int_entry(14); \
349 gpio_pad_int_entry(15); \
350 gpio_pad_int_entry(16); \
351 gpio_pad_int_entry(17); \
352 gpio_pad_int_entry(18); \
353 gpio_pad_int_entry(19); \
354 gpio_pad_int_entry(20); \
355 gpio_pad_int_entry(21); \
356 gpio_pad_int_entry(22); \
357 gpio_pad_int_entry(23); \
358 gpio_pad_int_entry(24); \
359 gpio_pad_int_entry(25); \
360 gpio_pad_int_entry(26); \
361 gpio_pad_int_entry(27); \
362 gpio_pad_int_entry(28); \
363 gpio_pad_int_entry(29); \
364 gpio_pad_int_entry(30); \
365 dc_underflow_int_entry(1); \
366 dc_underflow_int_entry(2); \
367 dc_underflow_int_entry(3); \
368 dc_underflow_int_entry(4); \
369 dc_underflow_int_entry(5); \
370 dc_underflow_int_entry(6); \
371 dummy_irq_entry(DC_IRQ_SOURCE_DMCU_SCP); \
372 dummy_irq_entry(DC_IRQ_SOURCE_VBIOS_SW); \
373
374 #define dcn35_irq_init_part_2() \
375 vupdate_no_lock_int_entry(0); \
376 vupdate_no_lock_int_entry(1); \
377 vupdate_no_lock_int_entry(2); \
378 vupdate_no_lock_int_entry(3); \
379 vblank_int_entry(0); \
380 vblank_int_entry(1); \
381 vblank_int_entry(2); \
382 vblank_int_entry(3); \
383 vline0_int_entry(0); \
384 vline0_int_entry(1); \
385 vline0_int_entry(2); \
386 vline0_int_entry(3); \
387 dummy_irq_entry(DC_IRQ_SOURCE_DC5_VLINE1); \
388 dummy_irq_entry(DC_IRQ_SOURCE_DC6_VLINE1); \
389 dmub_outbox_int_entry()
390
391 #define dcn35_irq_init() \
392 dcn35_irq_init_part_1(); \
393 dcn35_irq_init_part_2(); \
394
395 static struct irq_source_info irq_source_info_dcn35[DAL_IRQ_SOURCES_NUMBER] = {0};
396
397 static struct irq_service_funcs irq_service_funcs_dcn35 = {
398 .to_dal_irq_source = to_dal_irq_source_dcn35
399 };
400
dcn35_irq_construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)401 static void dcn35_irq_construct(
402 struct irq_service *irq_service,
403 struct irq_service_init_data *init_data)
404 {
405 struct dc_context *ctx = init_data->ctx;
406
407 #define REG_STRUCT irq_source_info_dcn35
408 dcn35_irq_init();
409
410 dal_irq_service_construct(irq_service, init_data);
411
412 irq_service->info = irq_source_info_dcn35;
413 irq_service->funcs = &irq_service_funcs_dcn35;
414 }
415
dal_irq_service_dcn35_create(struct irq_service_init_data * init_data)416 struct irq_service *dal_irq_service_dcn35_create(
417 struct irq_service_init_data *init_data)
418 {
419 struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
420 GFP_KERNEL);
421
422 if (!irq_service)
423 return NULL;
424
425 dcn35_irq_construct(irq_service, init_data);
426 return irq_service;
427 }
428