1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include "dm_services.h"
6 #include "include/logger_interface.h"
7 #include "../dce110/irq_service_dce110.h"
8
9 #include "dcn/dcn_4_1_0_offset.h"
10 #include "dcn/dcn_4_1_0_sh_mask.h"
11
12 #include "irq_service_dcn401.h"
13
14 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
15
16 #define DCN_BASE__INST0_SEG2 0x000034C0
17
to_dal_irq_source_dcn401(struct irq_service * irq_service,uint32_t src_id,uint32_t ext_id)18 static enum dc_irq_source to_dal_irq_source_dcn401(
19 struct irq_service *irq_service,
20 uint32_t src_id,
21 uint32_t ext_id)
22 {
23 switch (src_id) {
24 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
25 return DC_IRQ_SOURCE_VBLANK1;
26 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
27 return DC_IRQ_SOURCE_VBLANK2;
28 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
29 return DC_IRQ_SOURCE_VBLANK3;
30 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
31 return DC_IRQ_SOURCE_VBLANK4;
32 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
33 return DC_IRQ_SOURCE_VBLANK5;
34 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
35 return DC_IRQ_SOURCE_VBLANK6;
36 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
37 return DC_IRQ_SOURCE_DC1_VLINE0;
38 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
39 return DC_IRQ_SOURCE_DC2_VLINE0;
40 case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
41 return DC_IRQ_SOURCE_DC3_VLINE0;
42 case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
43 return DC_IRQ_SOURCE_DC4_VLINE0;
44 case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
45 return DC_IRQ_SOURCE_DC5_VLINE0;
46 case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
47 return DC_IRQ_SOURCE_DC6_VLINE0;
48 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
49 return DC_IRQ_SOURCE_PFLIP1;
50 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
51 return DC_IRQ_SOURCE_PFLIP2;
52 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
53 return DC_IRQ_SOURCE_PFLIP3;
54 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
55 return DC_IRQ_SOURCE_PFLIP4;
56 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
57 return DC_IRQ_SOURCE_PFLIP5;
58 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
59 return DC_IRQ_SOURCE_PFLIP6;
60 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
61 return DC_IRQ_SOURCE_VUPDATE1;
62 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
63 return DC_IRQ_SOURCE_VUPDATE2;
64 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
65 return DC_IRQ_SOURCE_VUPDATE3;
66 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
67 return DC_IRQ_SOURCE_VUPDATE4;
68 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
69 return DC_IRQ_SOURCE_VUPDATE5;
70 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
71 return DC_IRQ_SOURCE_VUPDATE6;
72 case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
73 return DC_IRQ_SOURCE_DMCUB_OUTBOX;
74
75 case DCN_1_0__SRCID__DC_HPD1_INT:
76 /* generic src_id for all HPD and HPDRX interrupts */
77 switch (ext_id) {
78 case DCN_1_0__CTXID__DC_HPD1_INT:
79 return DC_IRQ_SOURCE_HPD1;
80 case DCN_1_0__CTXID__DC_HPD2_INT:
81 return DC_IRQ_SOURCE_HPD2;
82 case DCN_1_0__CTXID__DC_HPD3_INT:
83 return DC_IRQ_SOURCE_HPD3;
84 case DCN_1_0__CTXID__DC_HPD4_INT:
85 return DC_IRQ_SOURCE_HPD4;
86 case DCN_1_0__CTXID__DC_HPD5_INT:
87 return DC_IRQ_SOURCE_HPD5;
88 case DCN_1_0__CTXID__DC_HPD6_INT:
89 return DC_IRQ_SOURCE_HPD6;
90 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
91 return DC_IRQ_SOURCE_HPD1RX;
92 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
93 return DC_IRQ_SOURCE_HPD2RX;
94 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
95 return DC_IRQ_SOURCE_HPD3RX;
96 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
97 return DC_IRQ_SOURCE_HPD4RX;
98 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
99 return DC_IRQ_SOURCE_HPD5RX;
100 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
101 return DC_IRQ_SOURCE_HPD6RX;
102 default:
103 return DC_IRQ_SOURCE_INVALID;
104 }
105 break;
106
107 default:
108 return DC_IRQ_SOURCE_INVALID;
109 }
110 }
111
hpd_ack(struct irq_service * irq_service,const struct irq_source_info * info)112 static bool hpd_ack(
113 struct irq_service *irq_service,
114 const struct irq_source_info *info)
115 {
116 uint32_t addr = info->status_reg;
117 uint32_t value = dm_read_reg(irq_service->ctx, addr);
118 uint32_t current_status =
119 get_reg_field_value(
120 value,
121 HPD0_DC_HPD_INT_STATUS,
122 DC_HPD_SENSE_DELAYED);
123
124 dal_irq_service_ack_generic(irq_service, info);
125
126 value = dm_read_reg(irq_service->ctx, info->enable_reg);
127
128 set_reg_field_value(
129 value,
130 current_status ? 0 : 1,
131 HPD0_DC_HPD_INT_CONTROL,
132 DC_HPD_INT_POLARITY);
133
134 dm_write_reg(irq_service->ctx, info->enable_reg, value);
135
136 return true;
137 }
138
139 static struct irq_source_info_funcs hpd_irq_info_funcs = {
140 .set = NULL,
141 .ack = hpd_ack
142 };
143
144 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
145 .set = NULL,
146 .ack = NULL
147 };
148
149 static struct irq_source_info_funcs pflip_irq_info_funcs = {
150 .set = NULL,
151 .ack = NULL
152 };
153
154 static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
155 .set = NULL,
156 .ack = NULL
157 };
158
159 static struct irq_source_info_funcs vblank_irq_info_funcs = {
160 .set = NULL,
161 .ack = NULL
162 };
163
164 static struct irq_source_info_funcs outbox_irq_info_funcs = {
165 .set = NULL,
166 .ack = NULL
167 };
168
169 static struct irq_source_info_funcs vline0_irq_info_funcs = {
170 .set = NULL,
171 .ack = NULL
172 };
173
174 #undef BASE_INNER
175 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
176
177 /* compile time expand base address. */
178 #define BASE(seg) \
179 BASE_INNER(seg)
180
181 #define SRI(reg_name, block, id)\
182 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
183 reg ## block ## id ## _ ## reg_name
184
185 #define SRI_DMUB(reg_name)\
186 BASE(reg ## reg_name ## _BASE_IDX) + \
187 reg ## reg_name
188
189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
190 .enable_reg = SRI(reg1, block, reg_num),\
191 .enable_mask = \
192 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
193 .enable_value = {\
194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
195 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
196 },\
197 .ack_reg = SRI(reg2, block, reg_num),\
198 .ack_mask = \
199 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
200 .ack_value = \
201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
202
203 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
204 .enable_reg = SRI_DMUB(reg1),\
205 .enable_mask = \
206 reg1 ## __ ## mask1 ## _MASK,\
207 .enable_value = {\
208 reg1 ## __ ## mask1 ## _MASK,\
209 ~reg1 ## __ ## mask1 ## _MASK \
210 },\
211 .ack_reg = SRI_DMUB(reg2),\
212 .ack_mask = \
213 reg2 ## __ ## mask2 ## _MASK,\
214 .ack_value = \
215 reg2 ## __ ## mask2 ## _MASK \
216
217 #define hpd_int_entry(reg_num)\
218 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
219 IRQ_REG_ENTRY(HPD, reg_num,\
220 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
221 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
222 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
223 .funcs = &hpd_irq_info_funcs\
224 }
225
226 #define hpd_rx_int_entry(reg_num)\
227 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
228 IRQ_REG_ENTRY(HPD, reg_num,\
229 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
230 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
231 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
232 .funcs = &hpd_rx_irq_info_funcs\
233 }
234 #define pflip_int_entry(reg_num)\
235 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
236 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
237 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
238 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
239 .funcs = &pflip_irq_info_funcs\
240 }
241
242 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
243 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
244 */
245 #define vupdate_no_lock_int_entry(reg_num)\
246 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
247 IRQ_REG_ENTRY(OTG, reg_num,\
248 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
249 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
250 .funcs = &vupdate_no_lock_irq_info_funcs\
251 }
252
253 #define vblank_int_entry(reg_num)\
254 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
255 IRQ_REG_ENTRY(OTG, reg_num,\
256 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
257 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
258 .funcs = &vblank_irq_info_funcs\
259 }
260 #define vline0_int_entry(reg_num)\
261 [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
262 IRQ_REG_ENTRY(OTG, reg_num,\
263 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
264 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
265 .funcs = &vline0_irq_info_funcs\
266 }
267 #define dmub_outbox_int_entry()\
268 [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
269 IRQ_REG_ENTRY_DMUB(\
270 DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
271 DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
272 .funcs = &outbox_irq_info_funcs\
273 }
274
275 #define dummy_irq_entry() \
276 {\
277 .funcs = &dummy_irq_info_funcs\
278 }
279
280 #define i2c_int_entry(reg_num) \
281 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
282
283 #define dp_sink_int_entry(reg_num) \
284 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
285
286 #define gpio_pad_int_entry(reg_num) \
287 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
288
289 #define dc_underflow_int_entry(reg_num) \
290 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
291
292 static struct irq_source_info_funcs dummy_irq_info_funcs = {
293 .set = dal_irq_service_dummy_set,
294 .ack = dal_irq_service_dummy_ack
295 };
296
297 static const struct irq_source_info
298 irq_source_info_dcn401[DAL_IRQ_SOURCES_NUMBER] = {
299 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
300 hpd_int_entry(0),
301 hpd_int_entry(1),
302 hpd_int_entry(2),
303 hpd_int_entry(3),
304 hpd_rx_int_entry(0),
305 hpd_rx_int_entry(1),
306 hpd_rx_int_entry(2),
307 hpd_rx_int_entry(3),
308 i2c_int_entry(1),
309 i2c_int_entry(2),
310 i2c_int_entry(3),
311 i2c_int_entry(4),
312 i2c_int_entry(5),
313 i2c_int_entry(6),
314 dp_sink_int_entry(1),
315 dp_sink_int_entry(2),
316 dp_sink_int_entry(3),
317 dp_sink_int_entry(4),
318 dp_sink_int_entry(5),
319 dp_sink_int_entry(6),
320 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
321 pflip_int_entry(0),
322 pflip_int_entry(1),
323 pflip_int_entry(2),
324 pflip_int_entry(3),
325 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
326 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
327 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
328 gpio_pad_int_entry(0),
329 gpio_pad_int_entry(1),
330 gpio_pad_int_entry(2),
331 gpio_pad_int_entry(3),
332 gpio_pad_int_entry(4),
333 gpio_pad_int_entry(5),
334 gpio_pad_int_entry(6),
335 gpio_pad_int_entry(7),
336 gpio_pad_int_entry(8),
337 gpio_pad_int_entry(9),
338 gpio_pad_int_entry(10),
339 gpio_pad_int_entry(11),
340 gpio_pad_int_entry(12),
341 gpio_pad_int_entry(13),
342 gpio_pad_int_entry(14),
343 gpio_pad_int_entry(15),
344 gpio_pad_int_entry(16),
345 gpio_pad_int_entry(17),
346 gpio_pad_int_entry(18),
347 gpio_pad_int_entry(19),
348 gpio_pad_int_entry(20),
349 gpio_pad_int_entry(21),
350 gpio_pad_int_entry(22),
351 gpio_pad_int_entry(23),
352 gpio_pad_int_entry(24),
353 gpio_pad_int_entry(25),
354 gpio_pad_int_entry(26),
355 gpio_pad_int_entry(27),
356 gpio_pad_int_entry(28),
357 gpio_pad_int_entry(29),
358 gpio_pad_int_entry(30),
359 dc_underflow_int_entry(1),
360 dc_underflow_int_entry(2),
361 dc_underflow_int_entry(3),
362 dc_underflow_int_entry(4),
363 dc_underflow_int_entry(5),
364 dc_underflow_int_entry(6),
365 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
366 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
367 vupdate_no_lock_int_entry(0),
368 vupdate_no_lock_int_entry(1),
369 vupdate_no_lock_int_entry(2),
370 vupdate_no_lock_int_entry(3),
371 vblank_int_entry(0),
372 vblank_int_entry(1),
373 vblank_int_entry(2),
374 vblank_int_entry(3),
375 vline0_int_entry(0),
376 vline0_int_entry(1),
377 vline0_int_entry(2),
378 vline0_int_entry(3),
379 [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
380 [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
381 dmub_outbox_int_entry(),
382 };
383
384 static const struct irq_service_funcs irq_service_funcs_dcn401 = {
385 .to_dal_irq_source = to_dal_irq_source_dcn401
386 };
387
dcn401_irq_construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)388 static void dcn401_irq_construct(
389 struct irq_service *irq_service,
390 struct irq_service_init_data *init_data)
391 {
392 dal_irq_service_construct(irq_service, init_data);
393
394 irq_service->info = irq_source_info_dcn401;
395 irq_service->funcs = &irq_service_funcs_dcn401;
396 }
397
dal_irq_service_dcn401_create(struct irq_service_init_data * init_data)398 struct irq_service *dal_irq_service_dcn401_create(
399 struct irq_service_init_data *init_data)
400 {
401 struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
402 GFP_KERNEL);
403
404 if (!irq_service)
405 return NULL;
406
407 dcn401_irq_construct(irq_service, init_data);
408 return irq_service;
409 }
410