1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "include/logger_interface.h"
29
30 #include "../dce110/irq_service_dce110.h"
31
32 #include "dcn/dcn_2_0_0_offset.h"
33 #include "dcn/dcn_2_0_0_sh_mask.h"
34 #include "navi10_ip_offset.h"
35
36
37 #include "irq_service_dcn20.h"
38
39 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
40
to_dal_irq_source_dcn20(struct irq_service * irq_service,uint32_t src_id,uint32_t ext_id)41 static enum dc_irq_source to_dal_irq_source_dcn20(
42 struct irq_service *irq_service,
43 uint32_t src_id,
44 uint32_t ext_id)
45 {
46 switch (src_id) {
47 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
48 return DC_IRQ_SOURCE_VBLANK1;
49 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
50 return DC_IRQ_SOURCE_VBLANK2;
51 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
52 return DC_IRQ_SOURCE_VBLANK3;
53 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
54 return DC_IRQ_SOURCE_VBLANK4;
55 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
56 return DC_IRQ_SOURCE_VBLANK5;
57 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
58 return DC_IRQ_SOURCE_VBLANK6;
59 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
60 return DC_IRQ_SOURCE_DC1_VLINE0;
61 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
62 return DC_IRQ_SOURCE_DC2_VLINE0;
63 case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
64 return DC_IRQ_SOURCE_DC3_VLINE0;
65 case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
66 return DC_IRQ_SOURCE_DC4_VLINE0;
67 case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
68 return DC_IRQ_SOURCE_DC5_VLINE0;
69 case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
70 return DC_IRQ_SOURCE_DC6_VLINE0;
71 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
72 return DC_IRQ_SOURCE_PFLIP1;
73 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
74 return DC_IRQ_SOURCE_PFLIP2;
75 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
76 return DC_IRQ_SOURCE_PFLIP3;
77 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
78 return DC_IRQ_SOURCE_PFLIP4;
79 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
80 return DC_IRQ_SOURCE_PFLIP5;
81 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
82 return DC_IRQ_SOURCE_PFLIP6;
83 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
84 return DC_IRQ_SOURCE_VUPDATE1;
85 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
86 return DC_IRQ_SOURCE_VUPDATE2;
87 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
88 return DC_IRQ_SOURCE_VUPDATE3;
89 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
90 return DC_IRQ_SOURCE_VUPDATE4;
91 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
92 return DC_IRQ_SOURCE_VUPDATE5;
93 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
94 return DC_IRQ_SOURCE_VUPDATE6;
95
96 case DCN_1_0__SRCID__DC_HPD1_INT:
97 /* generic src_id for all HPD and HPDRX interrupts */
98 switch (ext_id) {
99 case DCN_1_0__CTXID__DC_HPD1_INT:
100 return DC_IRQ_SOURCE_HPD1;
101 case DCN_1_0__CTXID__DC_HPD2_INT:
102 return DC_IRQ_SOURCE_HPD2;
103 case DCN_1_0__CTXID__DC_HPD3_INT:
104 return DC_IRQ_SOURCE_HPD3;
105 case DCN_1_0__CTXID__DC_HPD4_INT:
106 return DC_IRQ_SOURCE_HPD4;
107 case DCN_1_0__CTXID__DC_HPD5_INT:
108 return DC_IRQ_SOURCE_HPD5;
109 case DCN_1_0__CTXID__DC_HPD6_INT:
110 return DC_IRQ_SOURCE_HPD6;
111 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
112 return DC_IRQ_SOURCE_HPD1RX;
113 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
114 return DC_IRQ_SOURCE_HPD2RX;
115 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
116 return DC_IRQ_SOURCE_HPD3RX;
117 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
118 return DC_IRQ_SOURCE_HPD4RX;
119 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
120 return DC_IRQ_SOURCE_HPD5RX;
121 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
122 return DC_IRQ_SOURCE_HPD6RX;
123 default:
124 return DC_IRQ_SOURCE_INVALID;
125 }
126 break;
127
128 default:
129 return DC_IRQ_SOURCE_INVALID;
130 }
131 }
132
hpd_ack(struct irq_service * irq_service,const struct irq_source_info * info)133 static bool hpd_ack(
134 struct irq_service *irq_service,
135 const struct irq_source_info *info)
136 {
137 uint32_t addr = info->status_reg;
138 uint32_t value = dm_read_reg(irq_service->ctx, addr);
139 uint32_t current_status =
140 get_reg_field_value(
141 value,
142 HPD0_DC_HPD_INT_STATUS,
143 DC_HPD_SENSE_DELAYED);
144
145 dal_irq_service_ack_generic(irq_service, info);
146
147 value = dm_read_reg(irq_service->ctx, info->enable_reg);
148
149 set_reg_field_value(
150 value,
151 current_status ? 0 : 1,
152 HPD0_DC_HPD_INT_CONTROL,
153 DC_HPD_INT_POLARITY);
154
155 dm_write_reg(irq_service->ctx, info->enable_reg, value);
156
157 return true;
158 }
159
160 static struct irq_source_info_funcs hpd_irq_info_funcs = {
161 .set = NULL,
162 .ack = hpd_ack
163 };
164
165 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
166 .set = NULL,
167 .ack = NULL
168 };
169
170 static struct irq_source_info_funcs pflip_irq_info_funcs = {
171 .set = NULL,
172 .ack = NULL
173 };
174
175 static struct irq_source_info_funcs vblank_irq_info_funcs = {
176 .set = NULL,
177 .ack = NULL
178 };
179
180 static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
181 .set = NULL,
182 .ack = NULL
183 };
184
185 static struct irq_source_info_funcs vline0_irq_info_funcs = {
186 .set = NULL,
187 .ack = NULL
188 };
189
190 #undef BASE_INNER
191 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
192
193 /* compile time expand base address. */
194 #define BASE(seg) \
195 BASE_INNER(seg)
196
197
198 #define SRI(reg_name, block, id)\
199 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
200 mm ## block ## id ## _ ## reg_name
201
202
203 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
204 .enable_reg = SRI(reg1, block, reg_num),\
205 .enable_mask = \
206 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
207 .enable_value = {\
208 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
209 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
210 },\
211 .ack_reg = SRI(reg2, block, reg_num),\
212 .ack_mask = \
213 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
214 .ack_value = \
215 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
216
217
218
219 #define hpd_int_entry(reg_num)\
220 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
221 IRQ_REG_ENTRY(HPD, reg_num,\
222 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
223 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
224 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
225 .funcs = &hpd_irq_info_funcs\
226 }
227
228 #define hpd_rx_int_entry(reg_num)\
229 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
230 IRQ_REG_ENTRY(HPD, reg_num,\
231 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
232 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
233 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
234 .funcs = &hpd_rx_irq_info_funcs\
235 }
236 #define pflip_int_entry(reg_num)\
237 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
238 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
239 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
240 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
241 .funcs = &pflip_irq_info_funcs\
242 }
243
244 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
245 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
246 */
247 #define vupdate_no_lock_int_entry(reg_num)\
248 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
249 IRQ_REG_ENTRY(OTG, reg_num,\
250 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
251 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
252 .funcs = &vupdate_no_lock_irq_info_funcs\
253 }
254
255 #define vblank_int_entry(reg_num)\
256 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
257 IRQ_REG_ENTRY(OTG, reg_num,\
258 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
259 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
260 .funcs = &vblank_irq_info_funcs\
261 }
262
263 #define vline0_int_entry(reg_num)\
264 [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
265 IRQ_REG_ENTRY(OTG, reg_num,\
266 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
267 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
268 .funcs = &vline0_irq_info_funcs\
269 }
270
271 #define dummy_irq_entry() \
272 {\
273 .funcs = &dummy_irq_info_funcs\
274 }
275
276 #define i2c_int_entry(reg_num) \
277 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
278
279 #define dp_sink_int_entry(reg_num) \
280 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
281
282 #define gpio_pad_int_entry(reg_num) \
283 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
284
285 #define dc_underflow_int_entry(reg_num) \
286 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
287
288 static struct irq_source_info_funcs dummy_irq_info_funcs = {
289 .set = dal_irq_service_dummy_set,
290 .ack = dal_irq_service_dummy_ack
291 };
292
293 static const struct irq_source_info
294 irq_source_info_dcn20[DAL_IRQ_SOURCES_NUMBER] = {
295 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
296 hpd_int_entry(0),
297 hpd_int_entry(1),
298 hpd_int_entry(2),
299 hpd_int_entry(3),
300 hpd_int_entry(4),
301 hpd_int_entry(5),
302 hpd_rx_int_entry(0),
303 hpd_rx_int_entry(1),
304 hpd_rx_int_entry(2),
305 hpd_rx_int_entry(3),
306 hpd_rx_int_entry(4),
307 hpd_rx_int_entry(5),
308 i2c_int_entry(1),
309 i2c_int_entry(2),
310 i2c_int_entry(3),
311 i2c_int_entry(4),
312 i2c_int_entry(5),
313 i2c_int_entry(6),
314 dp_sink_int_entry(1),
315 dp_sink_int_entry(2),
316 dp_sink_int_entry(3),
317 dp_sink_int_entry(4),
318 dp_sink_int_entry(5),
319 dp_sink_int_entry(6),
320 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
321 pflip_int_entry(0),
322 pflip_int_entry(1),
323 pflip_int_entry(2),
324 pflip_int_entry(3),
325 pflip_int_entry(4),
326 pflip_int_entry(5),
327 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
328 gpio_pad_int_entry(0),
329 gpio_pad_int_entry(1),
330 gpio_pad_int_entry(2),
331 gpio_pad_int_entry(3),
332 gpio_pad_int_entry(4),
333 gpio_pad_int_entry(5),
334 gpio_pad_int_entry(6),
335 gpio_pad_int_entry(7),
336 gpio_pad_int_entry(8),
337 gpio_pad_int_entry(9),
338 gpio_pad_int_entry(10),
339 gpio_pad_int_entry(11),
340 gpio_pad_int_entry(12),
341 gpio_pad_int_entry(13),
342 gpio_pad_int_entry(14),
343 gpio_pad_int_entry(15),
344 gpio_pad_int_entry(16),
345 gpio_pad_int_entry(17),
346 gpio_pad_int_entry(18),
347 gpio_pad_int_entry(19),
348 gpio_pad_int_entry(20),
349 gpio_pad_int_entry(21),
350 gpio_pad_int_entry(22),
351 gpio_pad_int_entry(23),
352 gpio_pad_int_entry(24),
353 gpio_pad_int_entry(25),
354 gpio_pad_int_entry(26),
355 gpio_pad_int_entry(27),
356 gpio_pad_int_entry(28),
357 gpio_pad_int_entry(29),
358 gpio_pad_int_entry(30),
359 dc_underflow_int_entry(1),
360 dc_underflow_int_entry(2),
361 dc_underflow_int_entry(3),
362 dc_underflow_int_entry(4),
363 dc_underflow_int_entry(5),
364 dc_underflow_int_entry(6),
365 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
366 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
367 vupdate_no_lock_int_entry(0),
368 vupdate_no_lock_int_entry(1),
369 vupdate_no_lock_int_entry(2),
370 vupdate_no_lock_int_entry(3),
371 vupdate_no_lock_int_entry(4),
372 vupdate_no_lock_int_entry(5),
373 vblank_int_entry(0),
374 vblank_int_entry(1),
375 vblank_int_entry(2),
376 vblank_int_entry(3),
377 vblank_int_entry(4),
378 vblank_int_entry(5),
379 vline0_int_entry(0),
380 vline0_int_entry(1),
381 vline0_int_entry(2),
382 vline0_int_entry(3),
383 vline0_int_entry(4),
384 vline0_int_entry(5),
385 };
386
387 static const struct irq_service_funcs irq_service_funcs_dcn20 = {
388 .to_dal_irq_source = to_dal_irq_source_dcn20
389 };
390
dcn20_irq_construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)391 static void dcn20_irq_construct(
392 struct irq_service *irq_service,
393 struct irq_service_init_data *init_data)
394 {
395 dal_irq_service_construct(irq_service, init_data);
396
397 irq_service->info = irq_source_info_dcn20;
398 irq_service->funcs = &irq_service_funcs_dcn20;
399 }
400
dal_irq_service_dcn20_create(struct irq_service_init_data * init_data)401 struct irq_service *dal_irq_service_dcn20_create(
402 struct irq_service_init_data *init_data)
403 {
404 struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
405 GFP_KERNEL);
406
407 if (!irq_service)
408 return NULL;
409
410 dcn20_irq_construct(irq_service, init_data);
411 return irq_service;
412 }
413