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/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt7988a.dtsi83 infracfg: clock-controller@10001000 { label
84 compatible = "mediatek,mt7988-infracfg", "syscon";
111 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
112 <&infracfg CLK_INFRA_66M_PWM_HCK>,
113 <&infracfg CLK_INFRA_66M_PWM_CK1>,
114 <&infracfg CLK_INFRA_66M_PWM_CK2>,
115 <&infracfg CLK_INFRA_66M_PWM_CK3>,
116 <&infracfg CLK_INFRA_66M_PWM_CK4>,
117 <&infracfg CLK_INFRA_66M_PWM_CK5>,
118 <&infracfg CLK_INFRA_66M_PWM_CK6>,
[all …]
Dmt7981b.dtsi60 infracfg: clock-controller@10001000 { label
61 compatible = "mediatek,mt7981-infracfg", "syscon";
88 clocks = <&infracfg CLK_INFRA_PWM_STA>,
89 <&infracfg CLK_INFRA_PWM_HCK>,
90 <&infracfg CLK_INFRA_PWM1_CK>,
91 <&infracfg CLK_INFRA_PWM2_CK>,
92 <&infracfg CLK_INFRA_PWM3_CK>;
102 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
103 <&infracfg CLK_INFRA_UART0_CK>;
113 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
[all …]
Dmt8365.dtsi287 infracfg: syscon@10001000 { label
288 compatible = "mediatek,mt8365-infracfg", "syscon";
326 mediatek,infracfg = <&infracfg>;
327 mediatek,infracfg-nao = <&infracfg_nao>;
343 mediatek,infracfg = <&infracfg>;
361 clocks = <&infracfg CLK_IFR_APU_AXI>,
373 mediatek,infracfg = <&infracfg>;
384 mediatek,infracfg = <&infracfg>;
392 mediatek,infracfg = <&infracfg>;
398 <&infracfg CLK_IFR_AUDIO>,
[all …]
Dmt7986a.dtsi143 infracfg: infracfg@10001000 { label
144 compatible = "mediatek,mt7986-infracfg", "syscon";
203 <&infracfg CLK_INFRA_PWM_STA>,
204 <&infracfg CLK_INFRA_PWM1_CK>,
205 <&infracfg CLK_INFRA_PWM2_CK>;
228 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
241 clocks = <&infracfg CLK_INFRA_EIP97_CK>;
252 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
253 <&infracfg CLK_INFRA_UART0_CK>;
256 <&infracfg CLK_INFRA_UART0_SEL>;
[all …]
Dmt8183.dtsi742 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
750 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
758 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
766 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
774 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
782 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
790 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
798 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
809 infracfg: syscon@10001000 { label
810 compatible = "mediatek,mt8183-infracfg", "syscon";
[all …]
Dmt8167.dtsi26 infracfg: infracfg@10001000 { label
27 compatible = "mediatek,mt8167-infracfg", "syscon";
54 mediatek,infracfg = <&infracfg>;
80 mediatek,infracfg = <&infracfg>;
91 mediatek,infracfg = <&infracfg>;
99 mediatek,infracfg = <&infracfg>;
Dmt8192.dtsi459 infracfg: syscon@10001000 { label
460 compatible = "mediatek,mt8192-infracfg", "syscon";
512 <&infracfg CLK_INFRA_AUDIO_26M_B>,
513 <&infracfg CLK_INFRA_AUDIO>;
515 mediatek,infracfg = <&infracfg>;
521 clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
523 mediatek,infracfg = <&infracfg>;
538 mediatek,infracfg = <&infracfg>;
579 mediatek,infracfg = <&infracfg>;
593 mediatek,infracfg = <&infracfg>;
[all …]
Dmt7622.dtsi75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
90 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
213 infracfg: infracfg@10000000 { label
214 compatible = "mediatek,mt7622-infracfg",
225 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
227 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
250 infracfg = <&infracfg>;
259 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
302 clocks = <&infracfg CLK_INFRA_TRNG>;
621 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
[all …]
Dmt8173.dtsi159 clocks = <&infracfg CLK_INFRA_CA53SEL>,
174 clocks = <&infracfg CLK_INFRA_CA53SEL>,
189 clocks = <&infracfg CLK_INFRA_CA72SEL>,
204 clocks = <&infracfg CLK_INFRA_CA72SEL>,
355 infracfg: power-controller@10001000 { label
356 compatible = "mediatek,mt8173-infracfg", "syscon";
481 mediatek,infracfg = <&infracfg>;
515 mediatek,infracfg = <&infracfg>;
533 clocks = <&infracfg CLK_INFRA_CLK_13M>,
542 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
[all …]
Dmt8188.dtsi911 compatible = "mediatek,mt8188-infracfg-ao", "syscon";
964 mediatek,infracfg = <&infracfg_ao>;
1025 mediatek,infracfg = <&infracfg_ao>;
1044 mediatek,infracfg = <&infracfg_ao>;
1060 mediatek,infracfg = <&infracfg_ao>;
1068 mediatek,infracfg = <&infracfg_ao>;
1076 mediatek,infracfg = <&infracfg_ao>;
1087 mediatek,infracfg = <&infracfg_ao>;
1102 mediatek,infracfg = <&infracfg_ao>;
1140 mediatek,infracfg = <&infracfg_ao>;
[all …]
Dmt8516.dtsi57 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
70 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
83 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
96 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
188 infracfg: infracfg@10001000 { label
189 compatible = "mediatek,mt8516-infracfg", "syscon";
Dmt2712e.dtsi252 infracfg: clock-controller@10001000 { label
253 compatible = "mediatek,mt2712-infracfg", "syscon";
293 infracfg = <&infracfg>;
319 clocks = <&infracfg CLK_INFRA_AO_SPI1>;
330 clocks = <&infracfg CLK_INFRA_M4U>;
332 mediatek,infracfg = <&infracfg>;
348 clocks = <&infracfg CLK_INFRA_M4U>;
350 mediatek,infracfg = <&infracfg>;
663 <&infracfg CLK_INFRA_AO_SPI0>;
Dmt6795.dtsi275 infracfg: syscon@10001000 { label
276 compatible = "mediatek,mt6795-infracfg", "syscon";
327 mediatek,infracfg = <&infracfg>;
360 mediatek,infracfg = <&infracfg>;
401 resets = <&infracfg MT6795_INFRA_RST0_PMIC_WRAP_RST>;
427 clocks = <&infracfg CLK_INFRA_M4U>;
451 clocks = <&infracfg CLK_INFRA_GCE>;
951 clocks = <&infracfg CLK_INFRA_SMI>, <&mmsys CLK_MM_SMI_COMMON>;
965 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&infracfg CLK_INFRA_SMI>;
/linux-6.12.1/drivers/soc/mediatek/
Dmtk-infracfg.c28 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_set_bus_protection() argument
35 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, in mtk_infracfg_set_bus_protection()
38 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); in mtk_infracfg_set_bus_protection()
40 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_set_bus_protection()
59 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_clear_bus_protection() argument
66 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); in mtk_infracfg_clear_bus_protection()
68 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); in mtk_infracfg_clear_bus_protection()
70 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_clear_bus_protection()
79 struct regmap *infracfg; in mtk_infracfg_init() local
87 infracfg = syscon_regmap_lookup_by_compatible("mediatek,mt8192-infracfg"); in mtk_infracfg_init()
[all …]
/linux-6.12.1/drivers/net/wireless/mediatek/mt76/mt7615/
Dsoc.c23 dev->infracfg = syscon_regmap_lookup_by_phandle(np, "mediatek,infracfg"); in mt7622_wmac_init()
24 if (IS_ERR(dev->infracfg)) { in mt7622_wmac_init()
26 return PTR_ERR(dev->infracfg); in mt7622_wmac_init()
/linux-6.12.1/Documentation/devicetree/bindings/soc/mediatek/
Dscpsys.txt32 - infracfg: must contain a phandle to the infracfg controller
65 infracfg = <&infracfg>;
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dmtk-btcvsd-snd.txt7 - mediatek,infracfg: the phandles of INFRASYS
22 mediatek,infracfg = <&infrasys>;
/linux-6.12.1/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-mediatek.txt70 clocks = <&infracfg CLK_INFRA_CPUSEL>,
192 clocks = <&infracfg CLK_INFRA_CA53SEL>,
204 clocks = <&infracfg CLK_INFRA_CA53SEL>,
216 clocks = <&infracfg CLK_INFRA_CA72SEL>,
228 clocks = <&infracfg CLK_INFRA_CA72SEL>,
/linux-6.12.1/arch/arm/boot/dts/mediatek/
Dmt7629.dtsi81 infracfg: syscon@10000000 { label
82 compatible = "mediatek,mt7629-infracfg", "syscon";
102 infracfg = <&infracfg>;
133 clocks = <&infracfg CLK_INFRA_TRNG_PD>;
473 mediatek,infracfg = <&infracfg>;
Dmt7623.dtsi80 clocks = <&infracfg CLK_INFRA_CPUSEL>,
92 clocks = <&infracfg CLK_INFRA_CPUSEL>,
104 clocks = <&infracfg CLK_INFRA_CPUSEL>,
116 clocks = <&infracfg CLK_INFRA_CPUSEL>,
234 infracfg: syscon@10001000 { label
235 compatible = "mediatek,mt7623-infracfg",
236 "mediatek,mt2701-infracfg",
276 infracfg = <&infracfg>;
304 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
306 clocks = <&infracfg CLK_INFRA_PMICSPI>,
[all …]
Dmt8135.dtsi133 infracfg: infracfg@10001000 { label
136 compatible = "mediatek,mt8135-infracfg", "syscon";
184 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
Dmt7623n.dtsi108 clocks = <&infracfg CLK_INFRA_M4U>;
132 clocks = <&infracfg CLK_INFRA_SMI>,
134 <&infracfg CLK_INFRA_SMI>;
259 clocks = <&infracfg CLK_INFRA_CEC>;
Dmt2701.dtsi132 infracfg: syscon@10001000 { label
133 compatible = "mediatek,mt2701-infracfg", "syscon";
155 infracfg = <&infracfg>;
192 clocks = <&infracfg CLK_INFRA_SMI>,
194 <&infracfg CLK_INFRA_SMI>;
222 clocks = <&infracfg CLK_INFRA_M4U>;
434 clocks = <&infracfg CLK_INFRA_AUDIO>,
/linux-6.12.1/drivers/clk/mediatek/
DMakefile21 obj-$(CONFIG_COMMON_CLK_MT6795) += clk-mt6795-apmixedsys.o clk-mt6795-infracfg.o \
50 clk-mt7622-infracfg.o
59 obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o
63 obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
67 obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
77 obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173-apmixedsys.o clk-mt8173-infracfg.o \
/linux-6.12.1/drivers/pmdomain/mediatek/
Dmtk-scpsys.c153 struct regmap *infracfg; member
286 return mtk_infracfg_set_bus_protection(scp->infracfg, in scpsys_bus_protect_enable()
298 return mtk_infracfg_clear_bus_protection(scp->infracfg, in scpsys_bus_protect_disable()
459 scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in init_scp()
461 if (IS_ERR(scp->infracfg)) { in init_scp()
463 PTR_ERR(scp->infracfg)); in init_scp()
464 return ERR_CAST(scp->infracfg); in init_scp()

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