Lines Matching refs:infracfg
742 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
750 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
758 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
766 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
774 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
782 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
790 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
798 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
809 infracfg: syscon@10001000 { label
810 compatible = "mediatek,mt8183-infracfg", "syscon";
861 <&infracfg CLK_INFRA_AUDIO>,
862 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>;
869 mediatek,infracfg = <&infracfg>;
897 mediatek,infracfg = <&infracfg>;
919 mediatek,infracfg = <&infracfg>;
938 mediatek,infracfg = <&infracfg>;
949 mediatek,infracfg = <&infracfg>;
978 mediatek,infracfg = <&infracfg>;
988 mediatek,infracfg = <&infracfg>;
996 mediatek,infracfg = <&infracfg>;
1022 <&infracfg CLK_INFRA_PMIC_AP>;
1041 clocks = <&infracfg CLK_INFRA_SCPSYS>;
1069 clocks = <&infracfg CLK_INFRA_GCE>;
1077 clocks = <&infracfg CLK_INFRA_AUXADC>;
1088 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
1098 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
1108 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
1118 clocks = <&infracfg CLK_INFRA_I2C6>,
1119 <&infracfg CLK_INFRA_AP_DMA>;
1132 clocks = <&infracfg CLK_INFRA_I2C0>,
1133 <&infracfg CLK_INFRA_AP_DMA>;
1146 clocks = <&infracfg CLK_INFRA_I2C1>,
1147 <&infracfg CLK_INFRA_AP_DMA>,
1148 <&infracfg CLK_INFRA_I2C1_ARBITER>;
1161 clocks = <&infracfg CLK_INFRA_I2C2>,
1162 <&infracfg CLK_INFRA_AP_DMA>,
1163 <&infracfg CLK_INFRA_I2C2_ARBITER>;
1179 <&infracfg CLK_INFRA_SPI0>;
1188 clocks = <&infracfg CLK_INFRA_THERM>,
1189 <&infracfg CLK_INFRA_AUXADC>;
1191 resets = <&infracfg MT8183_INFRACFG_AO_THERM_SW_RST>;
1203 clocks = <&infracfg CLK_INFRA_THERM>;
1218 <&infracfg CLK_INFRA_DISP_PWM>;
1226 clocks = <&infracfg CLK_INFRA_PWM>,
1227 <&infracfg CLK_INFRA_PWM_HCLK>,
1228 <&infracfg CLK_INFRA_PWM1>,
1229 <&infracfg CLK_INFRA_PWM2>,
1230 <&infracfg CLK_INFRA_PWM3>,
1231 <&infracfg CLK_INFRA_PWM4>;
1241 clocks = <&infracfg CLK_INFRA_I2C3>,
1242 <&infracfg CLK_INFRA_AP_DMA>;
1258 <&infracfg CLK_INFRA_SPI1>;
1268 clocks = <&infracfg CLK_INFRA_I2C4>,
1269 <&infracfg CLK_INFRA_AP_DMA>;
1285 <&infracfg CLK_INFRA_SPI2>;
1298 <&infracfg CLK_INFRA_SPI3>;
1308 clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
1309 <&infracfg CLK_INFRA_AP_DMA>,
1310 <&infracfg CLK_INFRA_I2C1_ARBITER>;
1323 clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
1324 <&infracfg CLK_INFRA_AP_DMA>,
1325 <&infracfg CLK_INFRA_I2C2_ARBITER>;
1338 clocks = <&infracfg CLK_INFRA_I2C5>,
1339 <&infracfg CLK_INFRA_AP_DMA>,
1340 <&infracfg CLK_INFRA_I2C5_ARBITER>;
1353 clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
1354 <&infracfg CLK_INFRA_AP_DMA>,
1355 <&infracfg CLK_INFRA_I2C5_ARBITER>;
1371 <&infracfg CLK_INFRA_SPI4>;
1384 <&infracfg CLK_INFRA_SPI5>;
1394 clocks = <&infracfg CLK_INFRA_I2C7>,
1395 <&infracfg CLK_INFRA_AP_DMA>;
1408 clocks = <&infracfg CLK_INFRA_I2C8>,
1409 <&infracfg CLK_INFRA_AP_DMA>;
1425 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
1426 <&infracfg CLK_INFRA_USB>;
1440 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
1441 <&infracfg CLK_INFRA_USB>;
1473 <&infracfg CLK_INFRA_AUDIO>,
1474 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
1551 <&infracfg CLK_INFRA_MSDC0>,
1552 <&infracfg CLK_INFRA_MSDC0_SCK>;
1563 <&infracfg CLK_INFRA_MSDC1>,
1564 <&infracfg CLK_INFRA_MSDC1_SCK>;