Lines Matching refs:infracfg
143 infracfg: infracfg@10001000 { label
144 compatible = "mediatek,mt7986-infracfg", "syscon";
203 <&infracfg CLK_INFRA_PWM_STA>,
204 <&infracfg CLK_INFRA_PWM1_CK>,
205 <&infracfg CLK_INFRA_PWM2_CK>;
228 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
241 clocks = <&infracfg CLK_INFRA_EIP97_CK>;
252 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
253 <&infracfg CLK_INFRA_UART0_CK>;
256 <&infracfg CLK_INFRA_UART0_SEL>;
267 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
268 <&infracfg CLK_INFRA_UART1_CK>;
270 assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
280 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
281 <&infracfg CLK_INFRA_UART2_CK>;
283 assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
294 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
295 <&infracfg CLK_INFRA_AP_DMA_CK>;
310 <&infracfg CLK_INFRA_SPI0_CK>,
311 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
324 <&infracfg CLK_INFRA_SPI1_CK>,
325 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
334 clocks = <&infracfg CLK_INFRA_THERM_CK>,
335 <&infracfg CLK_INFRA_ADC_26M_CK>;
347 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
360 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
361 <&infracfg CLK_INFRA_IUSB_CK>,
362 <&infracfg CLK_INFRA_IUSB_133_CK>,
363 <&infracfg CLK_INFRA_IUSB_66M_CK>,
386 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
387 <&infracfg CLK_INFRA_MSDC_CK>,
388 <&infracfg CLK_INFRA_MSDC_133M_CK>,
389 <&infracfg CLK_INFRA_MSDC_66M_CK>;
407 clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
408 <&infracfg CLK_INFRA_IPCIE_CK>,
409 <&infracfg CLK_INFRA_IPCIER_CK>,
410 <&infracfg CLK_INFRA_IPCIEB_CK>;