Lines Matching refs:infracfg
287 infracfg: syscon@10001000 { label
288 compatible = "mediatek,mt8365-infracfg", "syscon";
326 mediatek,infracfg = <&infracfg>;
327 mediatek,infracfg-nao = <&infracfg_nao>;
343 mediatek,infracfg = <&infracfg>;
361 clocks = <&infracfg CLK_IFR_APU_AXI>,
373 mediatek,infracfg = <&infracfg>;
384 mediatek,infracfg = <&infracfg>;
392 mediatek,infracfg = <&infracfg>;
398 <&infracfg CLK_IFR_AUDIO>,
399 <&infracfg CLK_IFR_AUD_26M_BK>;
402 mediatek,infracfg = <&infracfg>;
411 mediatek,infracfg = <&infracfg>;
444 clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
445 <&infracfg CLK_IFR_PMIC_AP>,
446 <&infracfg CLK_IFR_PWRAP_SYS>,
447 <&infracfg CLK_IFR_PWRAP_TMR>;
483 infracfg_nao: infracfg@1020e000 {
484 compatible = "mediatek,mt8365-infracfg", "syscon";
492 clocks = <&infracfg CLK_IFR_TRNG>;
511 clocks = <&infracfg CLK_IFR_AP_DMA>;
520 clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
531 clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>;
542 clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>;
554 clocks = <&infracfg CLK_IFR_PWM_HCLK>,
555 <&infracfg CLK_IFR_PWM>,
556 <&infracfg CLK_IFR_PWM1>,
557 <&infracfg CLK_IFR_PWM2>,
558 <&infracfg CLK_IFR_PWM3>;
567 clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>;
579 clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>;
591 clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>;
606 <&infracfg CLK_IFR_SPI0>;
616 clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>;
631 <&infracfg CLK_IFR_SSUSB_REF>,
632 <&infracfg CLK_IFR_SSUSB_SYS>,
633 <&infracfg CLK_IFR_ICUSB>;
646 <&infracfg CLK_IFR_SSUSB_REF>,
647 <&infracfg CLK_IFR_SSUSB_SYS>,
648 <&infracfg CLK_IFR_ICUSB>,
649 <&infracfg CLK_IFR_SSUSB_XHCI>;
662 <&infracfg CLK_IFR_MSDC0_HCLK>,
663 <&infracfg CLK_IFR_MSDC0_SRC>;
674 <&infracfg CLK_IFR_MSDC1_HCLK>,
675 <&infracfg CLK_IFR_MSDC1_SRC>;
686 <&infracfg CLK_IFR_MSDC2_HCLK>,
687 <&infracfg CLK_IFR_MSDC2_SRC>,
688 <&infracfg CLK_IFR_MSDC2_BK>,
689 <&infracfg CLK_IFR_AP_MSDC0>;
698 mediatek,pericfg = <&infracfg>;
701 <&infracfg CLK_IFR_NIC_AXI>,
702 <&infracfg CLK_IFR_NIC_SLV_AXI>;