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/linux-6.12.1/drivers/clk/imx/
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
107 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ argument
109 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
115 #define imx_clk_pfd(name, parent_name, reg, idx) \ argument
116 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
118 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ argument
119 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
127 #define imx_clk_divider(name, parent, reg, shift, width) \ argument
128 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
[all …]
Dclk-busy.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
16 static int clk_busy_wait(void __iomem *reg, u8 shift) in clk_busy_wait() argument
20 while (readl_relaxed(reg) & (1 << shift)) in clk_busy_wait()
22 return -ETIMEDOUT; in clk_busy_wait()
30 void __iomem *reg; member
31 u8 shift; member
46 return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate); in clk_busy_divider_recalc_rate()
54 return busy->div_ops->round_rate(&busy->div.hw, rate, prate); in clk_busy_divider_round_rate()
63 ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate); in clk_busy_divider_set_rate()
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
13 reg = <0x4>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
[all …]
Domap2430-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-mux-clock";
13 reg = <0x78>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <2>;
27 reg = <0x78>;
[all …]
Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
[all …]
Domap2420-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-no-wait-gate-clock";
13 ti,bit-shift = <15>;
14 reg = <0x0070>;
18 #clock-cells = <0>;
19 compatible = "ti,composite-mux-clock";
21 ti,bit-shift = <8>;
22 reg = <0x0070>;
26 #clock-cells = <0>;
[all …]
Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
21 reg = <0x0108>;
[all …]
/linux-6.12.1/drivers/memory/tegra/
Dtegra114.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/memory/tegra114-mc.h>
20 .reg = 0x34c,
21 .shift = 0,
32 .reg = 0x228,
36 .reg = 0x2e8,
37 .shift = 0,
48 .reg = 0x228,
52 .reg = 0x2f4,
53 .shift = 0,
[all …]
Dtegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/memory/tegra210-mc.h>
21 .reg = 0x228,
25 .reg = 0x2e8,
26 .shift = 0,
37 .reg = 0x228,
41 .reg = 0x2f4,
42 .shift = 0,
53 .reg = 0x228,
57 .reg = 0x2e8,
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Dtegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/memory/tegra124-mc.h>
21 .reg = 0x34c,
22 .shift = 0,
33 .reg = 0x228,
37 .reg = 0x2e8,
38 .shift = 0,
49 .reg = 0x228,
53 .reg = 0x2f4,
54 .shift = 0,
[all …]
Dtegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/memory/tegra30-mc.h>
42 .reg = 0x34c,
43 .shift = 0,
55 .reg = 0x228,
59 .reg = 0x2e8,
60 .shift = 0,
72 .reg = 0x228,
76 .reg = 0x2f4,
77 .shift = 0,
[all …]
/linux-6.12.1/drivers/bus/
Dda8xx-mstpri.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * some changes (as is the case for the LCD controller on da850-lcdk - the
54 int reg; member
55 int shift; member
61 .reg = DA8XX_MSTPRI0_OFFSET,
62 .shift = 0,
66 .reg = DA8XX_MSTPRI0_OFFSET,
67 .shift = 4,
71 .reg = DA8XX_MSTPRI0_OFFSET,
72 .shift = 16,
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/linux-6.12.1/drivers/soc/aspeed/
Daspeed-uart-routing.c1 // SPDX-License-Identifier: GPL-2.0+
41 uint8_t reg; member
43 uint8_t shift; member
68 .reg = HICR9,
69 .shift = 8,
88 .reg = HICRA,
89 .shift = 28,
108 .reg = HICRA,
109 .shift = 25,
126 .reg = HICRA,
[all …]
/linux-6.12.1/arch/arm/mach-omap2/
Dvp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 * struct omap_vp_ops - per-VP operations
36 * struct omap_vp_common - register data common to all VDDs
37 * @vpconfig_erroroffset_mask: ERROROFFSET bitmask in the PRM_VP*_CONFIG reg
38 * @vpconfig_errorgain_mask: ERRORGAIN bitmask in the PRM_VP*_CONFIG reg
39 * @vpconfig_initvoltage_mask: INITVOLTAGE bitmask in the PRM_VP*_CONFIG reg
40 * @vpconfig_timeouten: TIMEOUT bitmask in the PRM_VP*_CONFIG reg
41 * @vpconfig_initvdd: INITVDD bitmask in the PRM_VP*_CONFIG reg
42 * @vpconfig_forceupdate: FORCEUPDATE bitmask in the PRM_VP*_CONFIG reg
43 * @vpconfig_vpenable: VPENABLE bitmask in the PRM_VP*_CONFIG reg
[all …]
/linux-6.12.1/drivers/regulator/
Dmax8998.c1 // SPDX-License-Identifier: GPL-2.0+
3 // max8998.c - Voltage regulator driver for the Maxim 8998
5 // Copyright (C) 2009-2010 Samsung Electronics
23 #include <linux/mfd/max8998-private.h>
44 int *reg, int *shift) in max8998_get_enable_register() argument
50 *reg = MAX8998_REG_ONOFF1; in max8998_get_enable_register()
51 *shift = 3 - (ldo - MAX8998_LDO2); in max8998_get_enable_register()
54 *reg = MAX8998_REG_ONOFF2; in max8998_get_enable_register()
55 *shift = 7 - (ldo - MAX8998_LDO6); in max8998_get_enable_register()
58 *reg = MAX8998_REG_ONOFF3; in max8998_get_enable_register()
[all …]
/linux-6.12.1/drivers/clk/
Dclk-axm5516.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/clk-axm5516.c
16 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/lsi,axm5516-clks.h>
22 * struct axxia_clk - Common struct to all Axxia clocks.
33 * struct axxia_pllclk - Axxia PLL generated clock.
35 * @reg: Offset into regmap for PLL control register
39 u32 reg; member
44 * axxia_pllclk_recalc - Calculate the PLL generated clock rate given the
55 regmap_read(aclk->regmap, pll->reg, &control); in axxia_pllclk_recalc()
[all …]
/linux-6.12.1/drivers/clk/meson/
Dparm.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 #define PMASK(width) GENMASK(width - 1, 0)
14 #define SETPMASK(width, shift) GENMASK(shift + width - 1, shift) argument
15 #define CLRPMASK(width, shift) (~SETPMASK(width, shift)) argument
17 #define PARM_GET(width, shift, reg) \ argument
18 (((reg) & SETPMASK(width, shift)) >> (shift))
19 #define PARM_SET(width, shift, reg, val) \ argument
20 (((reg) & CLRPMASK(width, shift)) | ((val) << (shift)))
22 #define MESON_PARM_APPLICABLE(p) (!!((p)->width))
26 u8 shift; member
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/linux-6.12.1/drivers/clk/sunxi-ng/
Dccu_nkmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
39 for (_k = nkmp->min_k; _k <= nkmp->max_k; _k++) { in ccu_nkmp_find_best()
40 for (_n = nkmp->min_n; _n <= nkmp->max_n; _n++) { in ccu_nkmp_find_best()
41 for (_m = nkmp->min_m; _m <= nkmp->max_m; _m++) { in ccu_nkmp_find_best()
42 for (_p = nkmp->min_p; _p <= nkmp->max_p; _p <<= 1) { in ccu_nkmp_find_best()
52 if ((rate - tmp_rate) < (rate - best_rate)) { in ccu_nkmp_find_best()
64 nkmp->n = best_n; in ccu_nkmp_find_best()
65 nkmp->k = best_k; in ccu_nkmp_find_best()
[all …]
/linux-6.12.1/sound/soc/codecs/
Dpcm6240.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2022 - 2024 Texas Instruments Incorporated
12 // Author: Shenghao Ding <shenghao-ding@ti.com>
63 .shift = 1,
64 .reg = ADC5120_REG_CH1_ANALOG_GAIN,
69 .shift = 1,
70 .reg = ADC5120_REG_CH2_ANALOG_GAIN,
78 .shift = 0,
79 .reg = ADC5120_REG_CH1_DIGITAL_GAIN,
84 .shift = 0,
[all …]
/linux-6.12.1/include/linux/
Dclk-provider.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
31 /* parents need enable during gate/ungate, set rate and re-parent */
42 * struct clk_rate_request - Structure encoding the clk constraints that
77 * struct clk_duty - Structure encoding the duty cycle ratio of a clock
88 * struct clk_ops - Callback operations for hardware clocks; these are to
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/linux-6.12.1/sound/pci/ac97/
Dac97_patch.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 #define AC97_SINGLE_VALUE(reg,shift,mask,invert) \ argument
11 ((reg) | ((shift) << 8) | ((shift) << 12) | ((mask) << 16) | \
13 #define AC97_PAGE_SINGLE_VALUE(reg,shift,mask,invert,page) \ argument
14 (AC97_SINGLE_VALUE(reg,shift,mask,invert) | (1<<25) | ((page) << 26))
15 #define AC97_SINGLE(xname, reg, shift, mask, invert) \ argument
19 .private_value = AC97_SINGLE_VALUE(reg, shift, mask, invert) }
20 #define AC97_PAGE_SINGLE(xname, reg, shift, mask, invert, page) \ argument
24 .private_value = AC97_PAGE_SINGLE_VALUE(reg, shift, mask, invert, page) }
25 #define AC97_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \ argument
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/linux-6.12.1/arch/arm64/lib/
Dinsn.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
14 #include <asm/debug-monitors.h>
27 int shift; in aarch64_get_imm_shift_mask() local
31 mask = BIT(26) - 1; in aarch64_get_imm_shift_mask()
32 shift = 0; in aarch64_get_imm_shift_mask()
35 mask = BIT(19) - 1; in aarch64_get_imm_shift_mask()
36 shift = 5; in aarch64_get_imm_shift_mask()
39 mask = BIT(16) - 1; in aarch64_get_imm_shift_mask()
40 shift = 5; in aarch64_get_imm_shift_mask()
[all …]
/linux-6.12.1/sound/soc/sprd/
Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
118 static void sprd_mcdt_update(struct sprd_mcdt_dev *mcdt, u32 reg, u32 val, in sprd_mcdt_update() argument
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update()
131 u32 reg = MCDT_DAC0_WTMK + channel * 4; in sprd_mcdt_dac_set_watermark() local
136 sprd_mcdt_update(mcdt, reg, water_mark, in sprd_mcdt_dac_set_watermark()
143 u32 reg = MCDT_ADC0_WTMK + channel * 4; in sprd_mcdt_adc_set_watermark() local
148 sprd_mcdt_update(mcdt, reg, water_mark, in sprd_mcdt_adc_set_watermark()
155 u32 shift = MCDT_DAC_DMA_SHIFT + channel; in sprd_mcdt_dac_dma_enable() local
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/linux-6.12.1/drivers/clk/mxs/
Dclk-frac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
13 * struct clk_frac - mxs fractional divider clock
15 * @reg: register address
16 * @shift: the divider bit shift
18 * @busy: busy bit shift
25 void __iomem *reg; member
26 u8 shift; member
40 div = readl_relaxed(frac->reg) >> frac->shift; in clk_frac_recalc_rate()
41 div &= (1 << frac->width) - 1; in clk_frac_recalc_rate()
[all …]
/linux-6.12.1/drivers/clk/x86/
Dclk-cgu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
8 #include <linux/clk-provider.h>
12 #include "clk-cgu.h"
14 #define GATE_HW_REG_STAT(reg) ((reg) + 0x0) argument
15 #define GATE_HW_REG_EN(reg) ((reg) + 0x4) argument
16 #define GATE_HW_REG_DIS(reg) ((reg) + 0x8) argument
29 if (list->div_flags & CLOCK_FLAG_VAL_INIT) in lgm_clk_register_fixed()
30 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed()
31 list->div_width, list->div_val); in lgm_clk_register_fixed()
[all …]

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