Lines Matching +full:reg +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/memory/tegra210-mc.h>
21 .reg = 0x228,
25 .reg = 0x2e8,
26 .shift = 0,
37 .reg = 0x228,
41 .reg = 0x2f4,
42 .shift = 0,
53 .reg = 0x228,
57 .reg = 0x2e8,
58 .shift = 16,
69 .reg = 0x228,
73 .reg = 0x2f4,
74 .shift = 16,
85 .reg = 0x228,
89 .reg = 0x2ec,
90 .shift = 0,
101 .reg = 0x228,
105 .reg = 0x2f8,
106 .shift = 0,
117 .reg = 0x228,
121 .reg = 0x2e0,
122 .shift = 0,
133 .reg = 0x228,
137 .reg = 0x2e4,
138 .shift = 0,
149 .reg = 0x228,
153 .reg = 0x2f0,
154 .shift = 0,
165 .reg = 0x228,
169 .reg = 0x2fc,
170 .shift = 0,
181 .reg = 0x228,
185 .reg = 0x318,
186 .shift = 0,
197 .reg = 0x228,
201 .reg = 0x310,
202 .shift = 0,
213 .reg = 0x228,
217 .reg = 0x310,
218 .shift = 16,
229 .reg = 0x228,
233 .reg = 0x328,
234 .shift = 0,
245 .reg = 0x228,
249 .reg = 0x344,
250 .shift = 0,
261 .reg = 0x228,
265 .reg = 0x344,
266 .shift = 16,
277 .reg = 0x228,
281 .reg = 0x350,
282 .shift = 0,
293 .reg = 0x320,
294 .shift = 0,
305 .reg = 0x22c,
309 .reg = 0x328,
310 .shift = 16,
321 .reg = 0x22c,
325 .reg = 0x2e0,
326 .shift = 16,
337 .reg = 0x22c,
341 .reg = 0x2e4,
342 .shift = 16,
353 .reg = 0x22c,
357 .reg = 0x318,
358 .shift = 16,
369 .reg = 0x22c,
373 .reg = 0x314,
374 .shift = 0,
385 .reg = 0x320,
386 .shift = 16,
397 .reg = 0x22c,
401 .reg = 0x348,
402 .shift = 0,
413 .reg = 0x22c,
417 .reg = 0x348,
418 .shift = 16,
429 .reg = 0x22c,
433 .reg = 0x350,
434 .shift = 16,
445 .reg = 0x230,
449 .reg = 0x370,
450 .shift = 0,
461 .reg = 0x230,
465 .reg = 0x374,
466 .shift = 0,
477 .reg = 0x230,
481 .reg = 0x374,
482 .shift = 16,
493 .reg = 0x230,
497 .reg = 0x37c,
498 .shift = 0,
509 .reg = 0x230,
513 .reg = 0x37c,
514 .shift = 16,
525 .reg = 0x230,
529 .reg = 0x380,
530 .shift = 0,
541 .reg = 0x230,
545 .reg = 0x380,
546 .shift = 16,
557 .reg = 0x230,
561 .reg = 0x384,
562 .shift = 0,
573 .reg = 0x230,
577 .reg = 0x388,
578 .shift = 0,
589 .reg = 0x230,
593 .reg = 0x388,
594 .shift = 16,
605 .reg = 0x230,
609 .reg = 0x390,
610 .shift = 0,
621 .reg = 0x230,
625 .reg = 0x390,
626 .shift = 16,
637 .reg = 0x230,
641 .reg = 0x3a4,
642 .shift = 0,
653 .reg = 0x230,
657 .reg = 0x3a4,
658 .shift = 16,
669 /* read-only */
670 .reg = 0x230,
674 .reg = 0x3c8,
675 .shift = 0,
686 /* read-only */
687 .reg = 0x230,
691 .reg = 0x3c8,
692 .shift = 16,
703 .reg = 0x230,
707 .reg = 0x2f0,
708 .shift = 16,
719 .reg = 0x234,
723 .reg = 0x3b8,
724 .shift = 0,
735 .reg = 0x234,
739 .reg = 0x3bc,
740 .shift = 0,
751 .reg = 0x234,
755 .reg = 0x3c0,
756 .shift = 0,
767 .reg = 0x234,
771 .reg = 0x3c4,
772 .shift = 0,
783 .reg = 0x234,
787 .reg = 0x3b8,
788 .shift = 16,
799 .reg = 0x234,
803 .reg = 0x3bc,
804 .shift = 16,
815 .reg = 0x234,
819 .reg = 0x3c0,
820 .shift = 16,
831 .reg = 0x234,
835 .reg = 0x3c4,
836 .shift = 16,
847 .reg = 0x234,
851 .reg = 0x394,
852 .shift = 0,
863 .reg = 0x234,
867 .reg = 0x394,
868 .shift = 16,
879 .reg = 0x234,
883 .reg = 0x398,
884 .shift = 0,
895 .reg = 0x234,
899 .reg = 0x3c8,
900 .shift = 0,
911 .reg = 0x234,
915 .reg = 0x3d8,
916 .shift = 0,
927 .reg = 0x234,
931 .reg = 0x3d8,
932 .shift = 16,
943 .reg = 0x234,
947 .reg = 0x3dc,
948 .shift = 0,
959 .reg = 0x234,
963 .reg = 0x3dc,
964 .shift = 16,
975 .reg = 0x234,
979 .reg = 0x3e4,
980 .shift = 0,
991 .reg = 0x234,
995 .reg = 0x3e4,
996 .shift = 16,
1007 .reg = 0xb98,
1011 .reg = 0x3e0,
1012 .shift = 0,
1023 .reg = 0xb98,
1027 .reg = 0x3e0,
1028 .shift = 16,
1039 .reg = 0xb98,
1043 .reg = 0x3a0,
1044 .shift = 0,
1055 .reg = 0xb98,
1059 .reg = 0x3a0,
1060 .shift = 16,
1071 .reg = 0xb98,
1075 .reg = 0x3ec,
1076 .shift = 0,
1087 .reg = 0xb98,
1091 .reg = 0x3ec,
1092 .shift = 16,
1103 .reg = 0xb98,
1107 .reg = 0x3f0,
1108 .shift = 0,
1119 .reg = 0xb98,
1123 .reg = 0x3f0,
1124 .shift = 16,
1135 /* read-only */
1136 .reg = 0xb98,
1140 .reg = 0x3e8,
1141 .shift = 0,
1152 /* read-only */
1153 .reg = 0xb98,
1157 .reg = 0x3e8,
1158 .shift = 16,
1167 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
1168 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1169 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1170 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1171 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1172 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1173 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
1174 { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
1175 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
1176 { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
1177 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1178 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
1179 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1180 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
1181 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1182 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1183 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
1184 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1185 { .name = "ppcs1", .swgroup = TEGRA_SWGROUP_PPCS1, .reg = 0x298 },
1186 { .name = "dc1", .swgroup = TEGRA_SWGROUP_DC1, .reg = 0xa88 },
1187 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
1188 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
1189 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
1190 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
1191 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
1192 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
1193 { .name = "ppcs2", .swgroup = TEGRA_SWGROUP_PPCS2, .reg = 0xab0 },
1194 { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
1195 { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
1196 { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
1197 { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
1198 { .name = "hc1", .swgroup = TEGRA_SWGROUP_HC1, .reg = 0xac4 },
1199 { .name = "se1", .swgroup = TEGRA_SWGROUP_SE1, .reg = 0xac8 },
1200 { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
1201 { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
1202 { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
1203 { .name = "tsec1", .swgroup = TEGRA_SWGROUP_TSEC1, .reg = 0xad8 },
1204 { .name = "tsecb1", .swgroup = TEGRA_SWGROUP_TSECB1, .reg = 0xadc },
1205 { .name = "nvdec1", .swgroup = TEGRA_SWGROUP_NVDEC1, .reg = 0xae0 },