Lines Matching +full:reg +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/memory/tegra114-mc.h>
20 .reg = 0x34c,
21 .shift = 0,
32 .reg = 0x228,
36 .reg = 0x2e8,
37 .shift = 0,
48 .reg = 0x228,
52 .reg = 0x2f4,
53 .shift = 0,
64 .reg = 0x228,
68 .reg = 0x2e8,
69 .shift = 16,
80 .reg = 0x228,
84 .reg = 0x2f4,
85 .shift = 16,
96 .reg = 0x228,
100 .reg = 0x2ec,
101 .shift = 0,
112 .reg = 0x228,
116 .reg = 0x2f8,
117 .shift = 0,
128 .reg = 0x228,
132 .reg = 0x300,
133 .shift = 0,
144 .reg = 0x228,
148 .reg = 0x308,
149 .shift = 0,
160 .reg = 0x228,
164 .reg = 0x308,
165 .shift = 16,
176 .reg = 0x228,
180 .reg = 0x2e4,
181 .shift = 0,
192 .reg = 0x228,
196 .reg = 0x2f0,
197 .shift = 0,
208 .reg = 0x228,
212 .reg = 0x2fc,
213 .shift = 0,
224 .reg = 0x228,
228 .reg = 0x334,
229 .shift = 0,
240 .reg = 0x228,
244 .reg = 0x33c,
245 .shift = 0,
256 .reg = 0x228,
260 .reg = 0x30c,
261 .shift = 0,
272 .reg = 0x228,
276 .reg = 0x318,
277 .shift = 0,
288 .reg = 0x228,
292 .reg = 0x310,
293 .shift = 0,
304 .reg = 0x228,
308 .reg = 0x310,
309 .shift = 16,
320 .reg = 0x228,
324 .reg = 0x334,
325 .shift = 16,
336 .reg = 0x228,
340 .reg = 0x328,
341 .shift = 0,
352 .reg = 0x228,
356 .reg = 0x344,
357 .shift = 0,
368 .reg = 0x228,
372 .reg = 0x344,
373 .shift = 16,
384 .reg = 0x22c,
388 .reg = 0x338,
389 .shift = 0,
400 .reg = 0x22c,
404 .reg = 0x354,
405 .shift = 0,
416 .reg = 0x22c,
420 .reg = 0x354,
421 .shift = 16,
432 .reg = 0x22c,
436 .reg = 0x358,
437 .shift = 0,
448 .reg = 0x22c,
452 .reg = 0x358,
453 .shift = 16,
464 .reg = 0x324,
465 .shift = 0,
476 .reg = 0x320,
477 .shift = 0,
488 .reg = 0x22c,
492 .reg = 0x300,
493 .shift = 16,
504 .reg = 0x22c,
508 .reg = 0x304,
509 .shift = 0,
520 .reg = 0x22c,
524 .reg = 0x304,
525 .shift = 16,
536 .reg = 0x22c,
540 .reg = 0x328,
541 .shift = 16,
552 .reg = 0x22c,
556 .reg = 0x364,
557 .shift = 0,
568 .reg = 0x22c,
572 .reg = 0x368,
573 .shift = 0,
584 .reg = 0x22c,
588 .reg = 0x368,
589 .shift = 16,
600 .reg = 0x22c,
604 .reg = 0x36c,
605 .shift = 0,
616 .reg = 0x22c,
620 .reg = 0x30c,
621 .shift = 16,
632 .reg = 0x22c,
636 .reg = 0x2e4,
637 .shift = 16,
648 .reg = 0x22c,
652 .reg = 0x338,
653 .shift = 16,
664 .reg = 0x22c,
668 .reg = 0x340,
669 .shift = 0,
680 .reg = 0x22c,
684 .reg = 0x318,
685 .shift = 16,
696 .reg = 0x22c,
700 .reg = 0x314,
701 .shift = 0,
712 .reg = 0x22c,
716 .reg = 0x31c,
717 .shift = 0,
728 .reg = 0x324,
729 .shift = 16,
740 .reg = 0x320,
741 .shift = 16,
752 .reg = 0x22c,
756 .reg = 0x348,
757 .shift = 0,
768 .reg = 0x22c,
772 .reg = 0x348,
773 .shift = 16,
784 .reg = 0x22c,
788 .reg = 0x35c,
789 .shift = 0,
800 .reg = 0x22c,
804 .reg = 0x35c,
805 .shift = 16,
816 .reg = 0x230,
820 .reg = 0x360,
821 .shift = 0,
832 .reg = 0x230,
836 .reg = 0x360,
837 .shift = 16,
848 .reg = 0x230,
852 .reg = 0x37c,
853 .shift = 0,
864 .reg = 0x230,
868 .reg = 0x37c,
869 .shift = 16,
880 .reg = 0x230,
884 .reg = 0x380,
885 .shift = 0,
896 .reg = 0x230,
900 .reg = 0x380,
901 .shift = 16,
912 .reg = 0x230,
916 .reg = 0x388,
917 .shift = 0,
928 .reg = 0x230,
932 .reg = 0x384,
933 .shift = 0,
944 .reg = 0x230,
948 .reg = 0x388,
949 .shift = 16,
960 .reg = 0x230,
964 .reg = 0x384,
965 .shift = 16,
976 .reg = 0x38c,
977 .shift = 0,
988 .reg = 0x38c,
989 .shift = 16,
1000 .reg = 0x230,
1004 .reg = 0x390,
1005 .shift = 0,
1016 .reg = 0x230,
1020 .reg = 0x390,
1021 .shift = 16,
1030 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1031 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1032 { .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
1033 { .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
1034 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1035 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
1036 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1037 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1038 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
1039 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1040 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
1041 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1042 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
1043 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1044 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1045 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },