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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dsilabs,si5351.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
19 - Alvin Šipraga <alsi@bang-olufsen.dk>
24 - silabs,si5351a # Si5351A, 20-QFN package
25 - silabs,si5351a-msop # Si5351A, 10-MSOP package
26 - silabs,si5351b # Si5351B, 20-QFN package
27 - silabs,si5351c # Si5351C, 20-QFN package
[all …]
Dsilabs,si5341.txt6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
20 The driver can be used in "as is" mode, reading the current settings from the
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
35 "silabs,si5341" - Si5341 A/B/C/D
36 "silabs,si5342" - Si5342 A/B/C/D
[all …]
/linux-6.12.1/drivers/clk/qcom/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
35 /* Skip if already enabled or in FSM mode */ in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
[all …]
Dclk-alpha-pll.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <linux/clk-provider.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
[all …]
Dclk-hfpll.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
12 #include "clk-regmap.h"
13 #include "clk-hfpll.h"
23 struct hfpll_data const *hd = h->d; in __clk_hfpll_init_once()
24 struct regmap *regmap = h->clkr.regmap; in __clk_hfpll_init_once()
26 if (likely(h->init_done)) in __clk_hfpll_init_once()
29 /* Configure PLL parameters for integer mode. */ in __clk_hfpll_init_once()
30 if (hd->config_val) in __clk_hfpll_init_once()
31 regmap_write(regmap, hd->config_reg, hd->config_val); in __clk_hfpll_init_once()
[all …]
/linux-6.12.1/arch/mips/boot/dts/qca/
Dar9331.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
17 clocks = <&pll ATH79_CLK_CPU>;
22 cpuintc: interrupt-controller {
23 compatible = "qca,ar7100-cpu-intc";
25 interrupt-controller;
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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dqca,ar71xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Oleksij Rempel <o.rempel@pengutronix.de>
18 - items:
19 - enum:
20 - qca,ar7100-eth # Atheros AR7100
21 - qca,ar7240-eth # Atheros AR7240
22 - qca,ar7241-eth # Atheros AR7241
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/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dadi,adau1701.txt5 - compatible: Should contain "adi,adau1701"
6 - reg: The i2c address. Value depends on the state of ADDR0
11 - reset-gpio: A GPIO spec to define which pin is connected to the
12 chip's !RESET pin. If specified, the driver will
13 assert a hardware reset at probe time.
14 - adi,pll-mode-gpios: An array of two GPIO specs to describe the GPIOs
15 the ADAU's PLL config pins are connected to.
19 - adi,pin-config: An array of 12 numerical values selecting one of the
23 - avdd-supply: Power supply for AVDD, providing 3.3V
24 - dvdd-supply: Power supply for DVDD, providing 3.3V
[all …]
/linux-6.12.1/sound/soc/fsl/
Dfsl_xcvr.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/reset.h>
19 #include "imx-pcm.h"
46 struct reset_control *reset; member
48 u32 mode; member
71 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
109 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in fsl_xcvr_arc_mode_put()
110 unsigned int *item = ucontrol->value.enumerated.item; in fsl_xcvr_arc_mode_put()
112 xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]); in fsl_xcvr_arc_mode_put()
123 ucontrol->value.enumerated.item[0] = xcvr->arc_mode; in fsl_xcvr_arc_mode_get()
[all …]
/linux-6.12.1/arch/arm/mach-davinci/
Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
49 /* Switch CPU PLL to bypass mode */ in davinci_pm_suspend()
56 /* Powerdown CPU PLL */ in davinci_pm_suspend()
73 /* put CPU PLL in reset */ in davinci_pm_suspend()
78 /* put CPU PLL in power down */ in davinci_pm_suspend()
83 /* wait for CPU PLL reset */ in davinci_pm_suspend()
86 /* bring CPU PLL out of reset */ in davinci_pm_suspend()
91 /* Wait for CPU PLL to lock */ in davinci_pm_suspend()
94 /* Remove CPU PLL from bypass mode */ in davinci_pm_suspend()
111 ret = -EINVAL; in davinci_pm_enter()
[all …]
Dsleep.S1 /* SPDX-License-Identifier: GPL-2.0-only */
37 * r3: contains virtual base DDR2 PLL controller
41 stmfd sp!, {r0-r12, lr} @ save registers on stack
46 ldmia r0, {r0-r4}
49 * Switch DDR to self-refresh mode.
77 /* Put the DDR PLL in bypass and power down */
83 /* Wait for PLL to switch to bypass */
88 /* Power down the PLL */
106 /* initialize the DDR PLL controller */
108 /* Put PLL in reset */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsa8540p-ride.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "sa8540p-pmics.dtsi"
17 compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
29 stdout-path = "serial0:115200n8";
34 regulators-0 {
35 compatible = "qcom,pm8150-rpmh-regulators";
36 qcom,pmic-id = "a";
[all …]
Dsa8155p-adp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9 #include <dt-bindings/gpio/gpio.h>
16 compatible = "qcom,sa8155p-adp", "qcom,sa8155p";
24 stdout-path = "serial0:115200n8";
27 vreg_3p3: vreg-3p3-regulator {
28 compatible = "regulator-fixed";
29 regulator-name = "vreg_3p3";
30 regulator-min-microvolt = <3300000>;
[all …]
Dsa8295p-adp.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
11 #include <dt-bindings/spmi/spmi.h>
12 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
15 #include "sa8540p-pmics.dtsi"
19 compatible = "qcom,sa8295p-adp", "qcom,sa8540p";
26 stdout-path = "serial0:115200n8";
29 dp2-connector {
[all …]
/linux-6.12.1/drivers/clk/bcm/
Dclk-iproc-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
19 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
20 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
24 /* number of delay loops waiting for PLL to lock */
75 struct iproc_pll *pll; member
90 return -EINVAL; in pll_calc_param()
92 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
102 vco_out->ndiv_int = ndiv_int; in pll_calc_param()
[all …]
Dclk-iproc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
17 #define bit_mask(width) ((1 << (width)) - 1)
22 /* PLL that requires gating through ASIU */
25 /* PLL that has fractional part of the NDIV */
29 * Some of the iProc PLL/clocks may have an ASIC bug that requires read back
36 * Some PLLs require the PLL SW override bit to be set before changes can be
37 * applied to the PLL
43 * the PLL control register
63 * clock frequencies. They have a user mode that allows the divider
[all …]
/linux-6.12.1/drivers/gpu/drm/msm/hdmi/
Dhdmi_phy_8x60.c1 // SPDX-License-Identifier: GPL-2.0-only
14 /* De-serializer delay D/C for non-lbk mode: */ in hdmi_phy_8x60_powerup()
29 /* No matter what, start from the power down mode: */ in hdmi_phy_8x60_powerup()
48 /* Turn PLL power on: */ in hdmi_phy_8x60_powerup()
56 /* Write to HIGH after PLL power down de-assert: */ in hdmi_phy_8x60_powerup()
63 /* Enable PLL lock detect, PLL lock det will go high after lock in hdmi_phy_8x60_powerup()
64 * Enable the re-time logic in hdmi_phy_8x60_powerup()
97 /* Assert RESET PHY from controller */ in hdmi_phy_8x60_powerdown()
101 /* De-assert RESET PHY from controller */ in hdmi_phy_8x60_powerdown()
111 /* Disable PLL */ in hdmi_phy_8x60_powerdown()
[all …]
/linux-6.12.1/include/linux/clk/
Danalogbits-wrpll-cln28hpc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2018-2019 SiFive, Inc.
19 * WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be
21 * WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset
22 * WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal
23 * feedback mode
24 * WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external
25 * feedback mode (not yet supported by this driver)
37 * struct wrpll_cfg - WRPLL configuration values
38 * @divr: reference divider value (6 bits), as presented to the PLL signals
[all …]
/linux-6.12.1/drivers/phy/freescale/
Dphy-fsl-lynx-28g.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2021-2022 NXP. */
24 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
26 /* Per PLL registers */
27 #define LYNX_28G_PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0) argument
31 #define LYNX_28G_PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4) argument
39 #define LYNX_28G_PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8) argument
55 /* Lane a Tx Reset Control Register */
73 /* Lane a Rx Reset Control Register */
134 struct lynx_28g_pll pll[LYNX_28G_NUM_PLL]; member
[all …]
/linux-6.12.1/drivers/gpu/drm/hisilicon/hibmc/
Dhibmc_drm_de.c1 // SPDX-License-Identifier: GPL-2.0-or-later
60 struct drm_framebuffer *fb = new_plane_state->fb; in hibmc_plane_atomic_check()
61 struct drm_crtc *crtc = new_plane_state->crtc; in hibmc_plane_atomic_check()
63 u32 src_w = new_plane_state->src_w >> 16; in hibmc_plane_atomic_check()
64 u32 src_h = new_plane_state->src_h >> 16; in hibmc_plane_atomic_check()
73 if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) { in hibmc_plane_atomic_check()
74 drm_dbg_atomic(plane->dev, "scale not support\n"); in hibmc_plane_atomic_check()
75 return -EINVAL; in hibmc_plane_atomic_check()
78 if (new_plane_state->crtc_x < 0 || new_plane_state->crtc_y < 0) { in hibmc_plane_atomic_check()
79 drm_dbg_atomic(plane->dev, "crtc_x/y of drm_plane state is invalid\n"); in hibmc_plane_atomic_check()
[all …]
/linux-6.12.1/arch/sparc/include/asm/
Dfhc.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 #define FHC_PREGS_RCS 0x10UL /* FHC Reset Control/Status Register */
31 #define FHC_RCS_POR 0x80000000 /* Last reset was a power cycle */
32 #define FHC_RCS_SPOR 0x40000000 /* Last reset was sw power on reset */
33 #define FHC_RCS_SXIR 0x20000000 /* Last reset was sw XIR reset */
34 #define FHC_RCS_BPOR 0x10000000 /* Last reset was due to POR button */
35 #define FHC_RCS_BXIR 0x08000000 /* Last reset was due to XIR button */
36 #define FHC_RCS_WEVENT 0x04000000 /* CPU reset was due to wakeup event */
38 #define FHC_RCS_FENAB 0x01000000 /* Fatal errors elicit system reset */
41 #define FHC_CONTROL_FRST 0x00080000 /* Fatal Error Reset Enable */
[all …]
/linux-6.12.1/drivers/clk/
Dclk-si5351.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-si5351.c: Skyworks / Silicon Labs Si5351A/B/C I2C Clock Generator
6 * Rabeeh Khoury <rabeeh@solid-run.com>
10 * https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
12 * https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/application-notes/AN619.pdf
18 #include <linux/clk-provider.h>
31 #include "clk-si5351.h"
61 struct si5351_hw_data pll[2]; member
88 ret = regmap_read(drvdata->regmap, reg, &val); in si5351_reg_read()
90 dev_err(&drvdata->client->dev, in si5351_reg_read()
[all …]
/linux-6.12.1/drivers/gpu/drm/stm/
Dlvds.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
4 * Author(s): Raphaël GALLAIS-POU <raphael.gallais-pou@foss.st.com> for STMicroelectronics.
16 #include <linux/clk-provider.h>
19 #include <linux/media-bus-format.h>
23 #include <linux/reset.h>
60 #define CR_LKMOD BIT(5) /* Link Mode, for both Links */
62 #define CR_LK1POL GENMASK(20, 16) /* Link-1 output Polarity */
63 #define CR_LK2POL GENMASK(25, 21) /* Link-2 output Polarity */
82 #define PHY_GCR_RSTZ BIT(24) /* LVDS PHY digital reset */
[all …]

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