Lines Matching +full:pll +full:- +full:reset +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
12 #include "clk-regmap.h"
13 #include "clk-hfpll.h"
23 struct hfpll_data const *hd = h->d; in __clk_hfpll_init_once()
24 struct regmap *regmap = h->clkr.regmap; in __clk_hfpll_init_once()
26 if (likely(h->init_done)) in __clk_hfpll_init_once()
29 /* Configure PLL parameters for integer mode. */ in __clk_hfpll_init_once()
30 if (hd->config_val) in __clk_hfpll_init_once()
31 regmap_write(regmap, hd->config_reg, hd->config_val); in __clk_hfpll_init_once()
32 regmap_write(regmap, hd->m_reg, 0); in __clk_hfpll_init_once()
33 regmap_write(regmap, hd->n_reg, 1); in __clk_hfpll_init_once()
35 if (hd->user_reg) { in __clk_hfpll_init_once()
36 u32 regval = hd->user_val; in __clk_hfpll_init_once()
42 if (hd->user_vco_mask && rate > hd->low_vco_max_rate) in __clk_hfpll_init_once()
43 regval |= hd->user_vco_mask; in __clk_hfpll_init_once()
44 regmap_write(regmap, hd->user_reg, regval); in __clk_hfpll_init_once()
48 if (hd->l_val) in __clk_hfpll_init_once()
49 regmap_write(regmap, hd->l_reg, hd->l_val); in __clk_hfpll_init_once()
51 if (hd->droop_reg) in __clk_hfpll_init_once()
52 regmap_write(regmap, hd->droop_reg, hd->droop_val); in __clk_hfpll_init_once()
54 h->init_done = true; in __clk_hfpll_init_once()
60 struct hfpll_data const *hd = h->d; in __clk_hfpll_enable()
61 struct regmap *regmap = h->clkr.regmap; in __clk_hfpll_enable()
66 /* Disable PLL bypass mode. */ in __clk_hfpll_enable()
67 regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL); in __clk_hfpll_enable()
71 * de-asserting the reset. Delay 10us just to be safe. in __clk_hfpll_enable()
75 /* De-assert active-low PLL reset. */ in __clk_hfpll_enable()
76 regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); in __clk_hfpll_enable()
78 /* Wait for PLL to lock. */ in __clk_hfpll_enable()
79 if (hd->status_reg) in __clk_hfpll_enable()
84 regmap_read_poll_timeout(regmap, hd->status_reg, val, in __clk_hfpll_enable()
85 !(val & BIT(hd->lock_bit)), 0, in __clk_hfpll_enable()
90 /* Enable PLL output. */ in __clk_hfpll_enable()
91 regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); in __clk_hfpll_enable()
94 /* Enable an already-configured HFPLL. */
99 struct hfpll_data const *hd = h->d; in clk_hfpll_enable()
100 struct regmap *regmap = h->clkr.regmap; in clk_hfpll_enable()
101 u32 mode; in clk_hfpll_enable() local
103 spin_lock_irqsave(&h->lock, flags); in clk_hfpll_enable()
104 regmap_read(regmap, hd->mode_reg, &mode); in clk_hfpll_enable()
105 if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL))) in clk_hfpll_enable()
107 spin_unlock_irqrestore(&h->lock, flags); in clk_hfpll_enable()
114 struct hfpll_data const *hd = h->d; in __clk_hfpll_disable()
115 struct regmap *regmap = h->clkr.regmap; in __clk_hfpll_disable()
118 * Disable the PLL output, disable test mode, enable the bypass mode, in __clk_hfpll_disable()
119 * and assert the reset. in __clk_hfpll_disable()
121 regmap_update_bits(regmap, hd->mode_reg, in __clk_hfpll_disable()
130 spin_lock_irqsave(&h->lock, flags); in clk_hfpll_disable()
132 spin_unlock_irqrestore(&h->lock, flags); in clk_hfpll_disable()
138 struct hfpll_data const *hd = h->d; in clk_hfpll_determine_rate()
141 req->rate = clamp(req->rate, hd->min_rate, hd->max_rate); in clk_hfpll_determine_rate()
143 rrate = DIV_ROUND_UP(req->rate, req->best_parent_rate) * req->best_parent_rate; in clk_hfpll_determine_rate()
144 if (rrate > hd->max_rate) in clk_hfpll_determine_rate()
145 rrate -= req->best_parent_rate; in clk_hfpll_determine_rate()
147 req->rate = rrate; in clk_hfpll_determine_rate()
159 struct hfpll_data const *hd = h->d; in clk_hfpll_set_rate()
160 struct regmap *regmap = h->clkr.regmap; in clk_hfpll_set_rate()
167 spin_lock_irqsave(&h->lock, flags); in clk_hfpll_set_rate()
169 enabled = __clk_is_enabled(hw->clk); in clk_hfpll_set_rate()
174 if (hd->user_reg && hd->user_vco_mask) { in clk_hfpll_set_rate()
175 regmap_read(regmap, hd->user_reg, &val); in clk_hfpll_set_rate()
176 if (rate <= hd->low_vco_max_rate) in clk_hfpll_set_rate()
177 val &= ~hd->user_vco_mask; in clk_hfpll_set_rate()
179 val |= hd->user_vco_mask; in clk_hfpll_set_rate()
180 regmap_write(regmap, hd->user_reg, val); in clk_hfpll_set_rate()
183 regmap_write(regmap, hd->l_reg, l_val); in clk_hfpll_set_rate()
188 spin_unlock_irqrestore(&h->lock, flags); in clk_hfpll_set_rate()
197 struct hfpll_data const *hd = h->d; in clk_hfpll_recalc_rate()
198 struct regmap *regmap = h->clkr.regmap; in clk_hfpll_recalc_rate()
201 regmap_read(regmap, hd->l_reg, &l_val); in clk_hfpll_recalc_rate()
209 struct hfpll_data const *hd = h->d; in clk_hfpll_init()
210 struct regmap *regmap = h->clkr.regmap; in clk_hfpll_init()
211 u32 mode, status; in clk_hfpll_init() local
213 regmap_read(regmap, hd->mode_reg, &mode); in clk_hfpll_init()
214 if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) { in clk_hfpll_init()
219 if (hd->status_reg) { in clk_hfpll_init()
220 regmap_read(regmap, hd->status_reg, &status); in clk_hfpll_init()
221 if (!(status & BIT(hd->lock_bit))) { in clk_hfpll_init()
223 __clk_get_name(hw->clk)); in clk_hfpll_init()
235 struct hfpll_data const *hd = h->d; in hfpll_is_enabled()
236 struct regmap *regmap = h->clkr.regmap; in hfpll_is_enabled()
237 u32 mode; in hfpll_is_enabled() local
239 regmap_read(regmap, hd->mode_reg, &mode); in hfpll_is_enabled()
240 mode &= 0x7; in hfpll_is_enabled()
241 return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL); in hfpll_is_enabled()