Lines Matching +full:pll +full:- +full:reset +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0 */
30 #define FHC_PREGS_RCS 0x10UL /* FHC Reset Control/Status Register */
31 #define FHC_RCS_POR 0x80000000 /* Last reset was a power cycle */
32 #define FHC_RCS_SPOR 0x40000000 /* Last reset was sw power on reset */
33 #define FHC_RCS_SXIR 0x20000000 /* Last reset was sw XIR reset */
34 #define FHC_RCS_BPOR 0x10000000 /* Last reset was due to POR button */
35 #define FHC_RCS_BXIR 0x08000000 /* Last reset was due to XIR button */
36 #define FHC_RCS_WEVENT 0x04000000 /* CPU reset was due to wakeup event */
38 #define FHC_RCS_FENAB 0x01000000 /* Fatal errors elicit system reset */
41 #define FHC_CONTROL_FRST 0x00080000 /* Fatal Error Reset Enable */
44 #define FHC_CONTROL_DCD 0x00008000 /* DC-->DC Converter Disable */
45 #define FHC_CONTROL_POFF 0x00004000 /* AC/DC Controller PLL Disable */
46 #define FHC_CONTROL_FOFF 0x00002000 /* FHC Controller PLL Disable */
47 #define FHC_CONTROL_AOFF 0x00001000 /* CPU A SRAM/SBD Low Power Mode */
48 #define FHC_CONTROL_BOFF 0x00000800 /* CPU B SRAM/SBD Low Power Mode */
62 #define FHC_BSR_NDIAG 0x00000040 /* Not in Diag Mode */
63 #define FHC_BSR_NTBED 0x00000020 /* Not in TestBED Mode */