Lines Matching +full:pll +full:- +full:reset +full:- +full:mode

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Copyright (C) 2018-2019 SiFive, Inc.
19  * WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be
21  * WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset
22  * WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal
23  *	feedback mode
24  * WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external
25  *	feedback mode (not yet supported by this driver)
37  * struct wrpll_cfg - WRPLL configuration values
38  * @divr: reference divider value (6 bits), as presented to the PLL signals
39  * @divf: feedback divider value (9 bits), as presented to the PLL signals
40  * @divq: output divider value (3 bits), as presented to the PLL signals
41  * @flags: PLL configuration flags.  See above for more information
42  * @range: PLL loop filter range.  See below for more information
44  * @parent_rate: PLL refclk rate for which values are valid
48  * @divr, @divq, @divq, @range represent what the PLL expects to see
50  * minus one.  @divq is a power-of-two divider; for example, 1 =
51  * divide-by-2 and 6 = divide-by-64.  0 is an invalid @divq value.
54  * record should be zero-initialized with the exception of the @flags