| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_cx0_phy.c | 1 // SPDX-License-Identifier: MIT
25 for ((__lane) = 0; (__lane) < 2; (__lane)++) \
28 #define INTEL_CX0_LANE0 BIT(0)
34 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_encoder_is_c10phy()
47 return 0; in lane_mask_to_lane()
60 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
73 drm_WARN_ON(&i915->drm, !enabled); in assert_dc_off()
79 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_program_msgbus_timer()
83 XELPDP_PORT_MSGBUS_TIMER(i915, encoder->port, lane), in intel_cx0_program_msgbus_timer()
100 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_begin()
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| /linux-6.12.1/drivers/clk/qcom/ |
| D | clk-alpha-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <linux/clk-provider.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
17 # define PLL_OUTCTRL BIT(0)
22 # define PLL_LOCK_COUNT_MASK 0x3f
24 # define PLL_BIAS_COUNT_MASK 0x3f
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
[all …]
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| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
20 #define PLL_OUTCTRL BIT(0)
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
37 return 0; in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
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| /linux-6.12.1/drivers/clk/tegra/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
24 #define PLL_BASE_DIVM_SHIFT 0
26 #define PLLU_POST_DIVP_MASK 0x1
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
35 #define PLL_MISC_VCOCON_SHIFT 0
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
41 #define PMC_PLLP_WB0_OVERRIDE 0xf8
50 #define PLLE_BASE_DIVCML_MASK 0xf
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| /linux-6.12.1/drivers/clk/mediatek/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-pll.h"
20 #define REG_CON0 0
23 #define CON0_BASE_EN BIT(0)
24 #define CON0_PWR_ON BIT(0)
35 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
37 return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0; in mtk_pll_is_prepared()
40 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, in __mtk_pll_recalc_rate() argument
43 int pcwbits = pll->data->pcwbits; in __mtk_pll_recalc_rate()
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| /linux-6.12.1/drivers/clk/rockchip/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
20 #define PLL_MODE_MASK 0x3
21 #define PLL_MODE_SLOW 0x0
22 #define PLL_MODE_NORM 0x1
23 #define PLL_MODE_DEEP 0x2
24 #define PLL_RK3328_MODE_MASK 0x1
51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
[all …]
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| /linux-6.12.1/drivers/clk/sprd/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Spreadtrum pll clock driver
13 #include "pll.h"
18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
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| /linux-6.12.1/drivers/clk/bcm/ |
| D | clk-iproc-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
19 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
20 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
24 /* number of delay loops waiting for PLL to lock */
32 KP_BAND_MID = 0,
75 struct iproc_pll *pll; member
90 return -EINVAL; in pll_calc_param()
92 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
[all …]
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| D | clk-iproc-armpll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
15 #define IPROC_CLK_MAX_FREQ_POLICY 0x3
16 #define IPROC_CLK_POLICY_FREQ_OFFSET 0x008
18 #define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK 0x7
20 #define IPROC_CLK_PLLARMA_OFFSET 0xc00
23 #define IPROC_CLK_PLLARMA_PDIV_MASK 0xf
25 #define IPROC_CLK_PLLARMA_NDIV_INT_MASK 0x3ff
27 #define IPROC_CLK_PLLARMB_OFFSET 0xc04
[all …]
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| /linux-6.12.1/drivers/clk/samsung/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * This file contains the utility functions to register the pll clocks.
15 #include <linux/clk-provider.h>
18 #include "clk-pll.h"
27 /* PLL enable control bit offset in @con_reg register */
29 /* PLL lock status bit offset in @con_reg register */
39 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
41 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
44 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
55 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate() local
[all …]
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| /linux-6.12.1/drivers/clk/meson/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * In the most basic form, a Meson PLL is composed as follows:
13 * PLL
14 * +--------------------------------+
16 * | +--+ |
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
20 * | | +--+ | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
[all …]
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| /linux-6.12.1/drivers/clk/imx/ |
| D | clk-pllv3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
17 #define PLL_NUM_OFFSET 0x10
18 #define PLL_DENOM_OFFSET 0x20
19 #define PLL_IMX7_NUM_OFFSET 0x20
20 #define PLL_IMX7_DENOM_OFFSET 0x30
22 #define PLL_VF610_NUM_OFFSET 0x20
23 #define PLL_VF610_DENOM_OFFSET 0x30
25 #define BM_PLL_POWER (0x1 << 12)
26 #define BM_PLL_LOCK (0x1 << 31)
[all …]
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| D | clk-pllv4.c | 1 // SPDX-License-Identifier: GPL-2.0+
11 #include <linux/clk-provider.h>
19 /* PLL Control Status Register (xPLLCSR) */
20 #define PLL_CSR_OFFSET 0x0
22 #define PLL_EN BIT(0)
24 /* PLL Configuration Register (xPLLCFG) */
25 #define PLL_CFG_OFFSET 0x08
26 #define IMX8ULP_PLL_CFG_OFFSET 0x10
28 #define BM_PLL_MULT (0x7f << 16)
30 /* PLL Numerator Register (xPLLNUM) */
[all …]
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| D | clk-fracn-gppll.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #define PLL_CTRL 0x0
21 #define POWERUP_MASK BIT(0)
23 #define PLL_ANA_PRG 0x10
24 #define PLL_SPREAD_SPECTRUM 0x30
26 #define PLL_NUMERATOR 0x40
29 #define PLL_DENOMINATOR 0x50
30 #define PLL_MFD_MASK GENMASK(29, 0)
32 #define PLL_DIV 0x60
[all …]
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| D | clk-pll14xx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2017-2018 NXP.
10 #include <linux/clk-provider.h>
20 #define GNRL_CTL 0x0
21 #define DIV_CTL0 0x4
22 #define DIV_CTL1 0x8
30 #define SDIV_MASK GENMASK(2, 0)
31 #define KDIV_MASK GENMASK(15, 0)
48 PLL_1416X_RATE(1800000000U, 225, 3, 0),
49 PLL_1416X_RATE(1600000000U, 200, 3, 0),
[all …]
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| /linux-6.12.1/drivers/video/fbdev/aty/ |
| D | mach64_ct.c | 1 // SPDX-License-Identifier: GPL-2.0
18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
51 * CLK = ----------------------
68 * XCLK The clock rate of the on-chip memory
75 * SCLK Multi-purpose clock
77 * - MCLK and XCLK use the same FB_DIV
78 * - VCLK0 .. VCLK3 use the same FB_DIV
[all …]
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| /linux-6.12.1/drivers/clk/visconti/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Toshiba Visconti PLL driver
12 #include <linux/clk-provider.h>
17 #include "pll.h"
29 #define PLL_CONF_REG 0x0000
30 #define PLL_CTRL_REG 0x0004
31 #define PLL_FRACMODE_REG 0x0010
32 #define PLL_INTIN_REG 0x0014
33 #define PLL_FRACIN_REG 0x0018
34 #define PLL_REFDIV_REG 0x001c
[all …]
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| /linux-6.12.1/drivers/clk/at91/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
17 #define PLL_DIV_MASK 0xff
20 #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
21 (layout)->mul_mask)
23 #define PLL_MUL_MASK(layout) ((layout)->mul_mask)
26 #define PLL_ICPR_MASK(id) (0xffff << PLL_ICPR_SHIFT(id))
27 #define PLL_MAX_COUNT 0x3f
52 return status & PLL_STATUS_MASK(id) ? 1 : 0; in clk_pll_ready()
57 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
[all …]
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| /linux-6.12.1/drivers/clk/sophgo/ |
| D | clk-cv18xx-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
11 #include "clk-cv18xx-pll.h"
36 struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); in ipll_recalc_rate() local
39 value = readl(pll->common.base + pll->pll_reg); in ipll_recalc_rate()
51 unsigned long best_rate = 0; in ipll_find_rate()
53 unsigned long pre_div_sel = 0, div_sel = 0, post_div_sel = 0; in ipll_find_rate()
58 for_each_pll_limit_range(pre, &limit->pre_div) { in ipll_find_rate()
59 for_each_pll_limit_range(div, &limit->div) { in ipll_find_rate()
60 for_each_pll_limit_range(post, &limit->post_div) { in ipll_find_rate()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi_phy_8996.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
33 /* pll mmio base */
81 static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll) in pll_get_phy() argument
83 return platform_get_drvdata(pll->pdev); in pll_get_phy()
86 static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset, in hdmi_pll_write() argument
89 writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
92 static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset) in hdmi_pll_read() argument
94 return readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
97 static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel, in hdmi_tx_chan_write() argument
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| D | hdmi_phy_8998.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
35 /* pll mmio base */
80 static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8998 *pll) in pll_get_phy() argument
82 return platform_get_drvdata(pll->pdev); in pll_get_phy()
85 static inline void hdmi_pll_write(struct hdmi_pll_8998 *pll, int offset, in hdmi_pll_write() argument
88 writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
91 static inline u32 hdmi_pll_read(struct hdmi_pll_8998 *pll, int offset) in hdmi_pll_read() argument
93 return readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
96 static inline void hdmi_tx_chan_write(struct hdmi_pll_8998 *pll, int channel, in hdmi_tx_chan_write() argument
[all …]
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| /linux-6.12.1/drivers/clk/pistachio/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
16 #define PLL_STATUS 0x0
17 #define PLL_STATUS_LOCK BIT(0)
19 #define PLL_CTRL1 0x4
20 #define PLL_CTRL1_REFDIV_SHIFT 0
21 #define PLL_CTRL1_REFDIV_MASK 0x3f
23 #define PLL_CTRL1_FBDIV_MASK 0xfff
25 #define PLL_INT_CTRL1_POSTDIV1_MASK 0x7
27 #define PLL_INT_CTRL1_POSTDIV2_MASK 0x7
[all …]
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| /linux-6.12.1/drivers/gpu/drm/sprd/ |
| D | megacores_pll.c | 1 // SPDX-License-Identifier: GPL-2.0
15 #define L 0
17 #define CLK 0
19 #define INFINITY 0xffffffff
22 #define AVERAGE(a, b) (min(a, b) + abs((b) - (a)) / 2)
30 static int dphy_calc_pll_param(struct dphy_pll *pll) in dphy_calc_pll_param() argument
38 pll->potential_fvco = pll->freq / khz; in dphy_calc_pll_param()
39 pll->ref_clk = PHY_REF_CLK / khz; in dphy_calc_pll_param()
41 for (i = 0; i < 4; ++i) { in dphy_calc_pll_param()
42 if (pll->potential_fvco >= VCO_BAND_LOW && in dphy_calc_pll_param()
[all …]
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| /linux-6.12.1/drivers/clk/baikal-t1/ |
| D | ccu-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU PLL interface driver
12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
20 #include <linux/clk-provider.h>
29 #include "ccu-pll.h"
31 #define CCU_PLL_CTL 0x000
32 #define CCU_PLL_CTL_EN BIT(0)
42 #define CCU_PLL_CTL1 0x004
88 static int ccu_pll_reset(struct ccu_pll *pll, unsigned long ref_clk, in ccu_pll_reset() argument
97 regmap_update_bits(pll->sys_regs, pll->reg_ctl, in ccu_pll_reset()
[all …]
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| /linux-6.12.1/drivers/clk/st/ |
| D | clkgen-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/clk-provider.h>
24 * PLL configuration register bits for PLL3200 C32
26 #define C32_NDIV_MASK (0xff)
27 #define C32_IDF_MASK (0x7)
28 #define C32_ODF_MASK (0x3f)
29 #define C32_LDF_MASK (0x7f)
30 #define C32_CP_MASK (0x1f)
35 * PLL configuration register bits for PLL4600 C28
37 #define C28_NDIV_MASK (0xff)
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