1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #define PLL_CTRL		0x0
21 #define POWERUP_MASK		BIT(0)
23 #define PLL_ANA_PRG		0x10
24 #define PLL_SPREAD_SPECTRUM	0x30
26 #define PLL_NUMERATOR		0x40
29 #define PLL_DENOMINATOR		0x50
30 #define PLL_MFD_MASK		GENMASK(29, 0)
32 #define PLL_DIV			0x60
35 #define PLL_ODIV_MASK		GENMASK(7, 0)
37 #define PLL_DFS_CTRL(x)		(0x70 + (x) * 0x10)
39 #define PLL_STATUS		0xF0
40 #define LOCK_STATUS		BIT(0)
42 #define DFS_STATUS		0xF4
60 		.mfn	=	0,				\
61 		.mfd	=	0,				\
82 	PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
83 	PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
84 	PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
86 	PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
87 	PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
88 	PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
89 	PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
90 	PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
91 	PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
125 imx_get_pll_settings(struct clk_fracn_gppll *pll, unsigned long rate)  in imx_get_pll_settings()  argument
127 	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;  in imx_get_pll_settings()
130 	for (i = 0; i < pll->rate_count; i++)  in imx_get_pll_settings()
140 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_round_rate()  local
141 	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;  in clk_fracn_gppll_round_rate()
145 	for (i = 0; i < pll->rate_count; i++)  in clk_fracn_gppll_round_rate()
150 	return rate_table[pll->rate_count - 1].rate;  in clk_fracn_gppll_round_rate()
155 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_recalc_rate()  local
156 	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;  in clk_fracn_gppll_recalc_rate()
160 	long rate = 0;  in clk_fracn_gppll_recalc_rate()
163 	pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR);  in clk_fracn_gppll_recalc_rate()
166 	pll_denominator = readl_relaxed(pll->base + PLL_DENOMINATOR);  in clk_fracn_gppll_recalc_rate()
169 	pll_div = readl_relaxed(pll->base + PLL_DIV);  in clk_fracn_gppll_recalc_rate()
177 	 * the frac part. So find the accurate pll rate from the table  in clk_fracn_gppll_recalc_rate()
181 	for (i = 0; i < pll->rate_count; i++) {  in clk_fracn_gppll_recalc_rate()
195 	case 0:  in clk_fracn_gppll_recalc_rate()
205 	if (pll->flags & CLK_FRACN_GPPLL_INTEGER) {  in clk_fracn_gppll_recalc_rate()
218 static int clk_fracn_gppll_wait_lock(struct clk_fracn_gppll *pll)  in clk_fracn_gppll_wait_lock()  argument
222 	return readl_poll_timeout(pll->base + PLL_STATUS, val,  in clk_fracn_gppll_wait_lock()
223 				  val & LOCK_STATUS, 0, LOCK_TIMEOUT_US);  in clk_fracn_gppll_wait_lock()
229 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_set_rate()  local
234 	rate = imx_get_pll_settings(pll, drate);  in clk_fracn_gppll_set_rate()
236 	/* Hardware control select disable. PLL is control by register */  in clk_fracn_gppll_set_rate()
237 	tmp = readl_relaxed(pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
239 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
242 	tmp = readl_relaxed(pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
244 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
248 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
252 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
254 	pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv |  in clk_fracn_gppll_set_rate()
255 		FIELD_PREP(PLL_MFI_MASK, rate->mfi);  in clk_fracn_gppll_set_rate()
256 	writel_relaxed(pll_div, pll->base + PLL_DIV);  in clk_fracn_gppll_set_rate()
257 	if (pll->flags & CLK_FRACN_GPPLL_FRACN) {  in clk_fracn_gppll_set_rate()
258 		writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR);  in clk_fracn_gppll_set_rate()
259 		writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR);  in clk_fracn_gppll_set_rate()
262 	/* Wait for 5us according to fracn mode pll doc */  in clk_fracn_gppll_set_rate()
267 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
270 	ret = clk_fracn_gppll_wait_lock(pll);  in clk_fracn_gppll_set_rate()
276 	writel_relaxed(tmp, pll->base + PLL_CTRL);  in clk_fracn_gppll_set_rate()
278 	ana_mfn = readl_relaxed(pll->base + PLL_STATUS);  in clk_fracn_gppll_set_rate()
281 	WARN(ana_mfn != rate->mfn, "ana_mfn != rate->mfn\n");  in clk_fracn_gppll_set_rate()
283 	return 0;  in clk_fracn_gppll_set_rate()
288 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_prepare()  local
292 	val = readl_relaxed(pll->base + PLL_CTRL);  in clk_fracn_gppll_prepare()
294 		return 0;  in clk_fracn_gppll_prepare()
296 	if (pll->flags & CLK_FRACN_GPPLL_FRACN)  in clk_fracn_gppll_prepare()
297 		writel_relaxed(readl_relaxed(pll->base + PLL_NUMERATOR),  in clk_fracn_gppll_prepare()
298 			       pll->base + PLL_NUMERATOR);  in clk_fracn_gppll_prepare()
301 	writel_relaxed(val, pll->base + PLL_CTRL);  in clk_fracn_gppll_prepare()
304 	writel_relaxed(val, pll->base + PLL_CTRL);  in clk_fracn_gppll_prepare()
307 	writel_relaxed(val, pll->base + PLL_CTRL);  in clk_fracn_gppll_prepare()
309 	ret = clk_fracn_gppll_wait_lock(pll);  in clk_fracn_gppll_prepare()
314 	writel_relaxed(val, pll->base + PLL_CTRL);  in clk_fracn_gppll_prepare()
316 	return 0;  in clk_fracn_gppll_prepare()
321 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_is_prepared()  local
324 	val = readl_relaxed(pll->base + PLL_CTRL);  in clk_fracn_gppll_is_prepared()
326 	return (val & POWERUP_MASK) ? 1 : 0;  in clk_fracn_gppll_is_prepared()
331 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);  in clk_fracn_gppll_unprepare()  local
334 	val = readl_relaxed(pll->base + PLL_CTRL);  in clk_fracn_gppll_unprepare()
336 	writel_relaxed(val, pll->base + PLL_CTRL);  in clk_fracn_gppll_unprepare()
353 	struct clk_fracn_gppll *pll;  in _imx_clk_fracn_gppll()  local
358 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in _imx_clk_fracn_gppll()
359 	if (!pll)  in _imx_clk_fracn_gppll()
360 		return ERR_PTR(-ENOMEM);  in _imx_clk_fracn_gppll()
363 	init.flags = pll_clk->flags;  in _imx_clk_fracn_gppll()
368 	pll->base = base;  in _imx_clk_fracn_gppll()
369 	pll->hw.init = &init;  in _imx_clk_fracn_gppll()
370 	pll->rate_table = pll_clk->rate_table;  in _imx_clk_fracn_gppll()
371 	pll->rate_count = pll_clk->rate_count;  in _imx_clk_fracn_gppll()
372 	pll->flags = pll_flags;  in _imx_clk_fracn_gppll()
374 	hw = &pll->hw;  in _imx_clk_fracn_gppll()
378 		pr_err("%s: failed to register pll %s %d\n", __func__, name, ret);  in _imx_clk_fracn_gppll()
379 		kfree(pll);  in _imx_clk_fracn_gppll()