Lines Matching +full:pll +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
35 /* pll mmio base */
80 static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8998 *pll) in pll_get_phy() argument
82 return platform_get_drvdata(pll->pdev); in pll_get_phy()
85 static inline void hdmi_pll_write(struct hdmi_pll_8998 *pll, int offset, in hdmi_pll_write() argument
88 writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
91 static inline u32 hdmi_pll_read(struct hdmi_pll_8998 *pll, int offset) in hdmi_pll_read() argument
93 return readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
96 static inline void hdmi_tx_chan_write(struct hdmi_pll_8998 *pll, int channel, in hdmi_tx_chan_write() argument
99 writel(data, pll->mmio_qserdes_tx[channel] + offset); in hdmi_tx_chan_write()
105 if ((frac_start != 0) || gen_ssc) in pll_get_cpctrl()
106 return 0x8; in pll_get_cpctrl()
108 return 0x30; in pll_get_cpctrl()
113 if ((frac_start != 0) || gen_ssc) in pll_get_rctrl()
114 return 0x16; in pll_get_rctrl()
116 return 0x18; in pll_get_rctrl()
121 if ((frac_start != 0) || gen_ssc) in pll_get_cctrl()
122 return 0x34; in pll_get_cctrl()
124 return 0x2; in pll_get_cctrl()
133 if ((frac_start != 0) || gen_ssc) in pll_get_integloop_gain()
134 base = 0x3F; in pll_get_integloop_gain()
136 base = 0xC4; in pll_get_integloop_gain()
138 base <<= (digclk_divsel == 2 ? 1 : 0); in pll_get_integloop_gain()
153 return dividend - 1; in pll_get_pll_cmp()
162 u32 const band_list[] = {0, 1, 2, 3}; in pll_get_post_div()
167 u32 half_rate_mode = 0; in pll_get_post_div()
171 u32 found_hsclk_divsel = 0, found_vco_ratio; in pll_get_post_div()
180 optimal_index = -1; in pll_get_post_div()
181 list_elements = 0; in pll_get_post_div()
183 for (i = 0; i < sz_ratio; i++) { in pll_get_post_div()
184 for (j = 0; j < sz_band; j++) { in pll_get_post_div()
192 for (k = 0; k < ARRAY_SIZE(freq_list); k++) { in pll_get_post_div()
226 if (optimal_index == -1) { in pll_get_post_div()
231 return -EINVAL; in pll_get_post_div()
244 found_hsclk_divsel = 0; in pll_get_post_div()
275 pd->vco_freq = found_vco_freq; in pll_get_post_div()
276 pd->tx_band_sel = found_tx_band_sel; in pll_get_post_div()
277 pd->vco_ratio = found_vco_ratio; in pll_get_post_div()
278 pd->hsclk_divsel = found_hsclk_divsel; in pll_get_post_div()
280 return 0; in pll_get_post_div()
314 frac_start -= dec_start * (1 << 20); in pll_calculate()
331 cfg->com_svs_mode_clk_sel = 1; in pll_calculate()
333 cfg->com_svs_mode_clk_sel = 2; in pll_calculate()
335 cfg->com_hsclk_sel = (0x20 | pd.hsclk_divsel); in pll_calculate()
336 cfg->com_pll_cctrl_mode0 = cctrl; in pll_calculate()
337 cfg->com_pll_rctrl_mode0 = rctrl; in pll_calculate()
338 cfg->com_cp_ctrl_mode0 = cpctrl; in pll_calculate()
339 cfg->com_dec_start_mode0 = dec_start; in pll_calculate()
340 cfg->com_div_frac_start1_mode0 = (frac_start & 0xff); in pll_calculate()
341 cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8); in pll_calculate()
342 cfg->com_div_frac_start3_mode0 = ((frac_start & 0xf0000) >> 16); in pll_calculate()
343 cfg->com_integloop_gain0_mode0 = (integloop_gain & 0xff); in pll_calculate()
344 cfg->com_integloop_gain1_mode0 = ((integloop_gain & 0xf00) >> 8); in pll_calculate()
345 cfg->com_lock_cmp1_mode0 = (pll_cmp & 0xff); in pll_calculate()
346 cfg->com_lock_cmp2_mode0 = ((pll_cmp & 0xff00) >> 8); in pll_calculate()
347 cfg->com_lock_cmp3_mode0 = ((pll_cmp & 0x30000) >> 16); in pll_calculate()
348 cfg->com_lock_cmp_en = 0x0; in pll_calculate()
349 cfg->com_core_clk_en = 0x2c; in pll_calculate()
350 cfg->com_coreclk_div_mode0 = HDMI_CORECLK_DIV; in pll_calculate()
351 cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x5 : 0x4; in pll_calculate()
353 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) in pll_calculate()
354 cfg->tx_lx_tx_band[i] = pd.tx_band_sel; in pll_calculate()
357 cfg->tx_lx_tx_drv_lvl[0] = 0x0f; in pll_calculate()
358 cfg->tx_lx_tx_drv_lvl[1] = 0x0f; in pll_calculate()
359 cfg->tx_lx_tx_drv_lvl[2] = 0x0f; in pll_calculate()
360 cfg->tx_lx_tx_drv_lvl[3] = 0x0f; in pll_calculate()
361 cfg->tx_lx_tx_emp_post1_lvl[0] = 0x03; in pll_calculate()
362 cfg->tx_lx_tx_emp_post1_lvl[1] = 0x02; in pll_calculate()
363 cfg->tx_lx_tx_emp_post1_lvl[2] = 0x03; in pll_calculate()
364 cfg->tx_lx_tx_emp_post1_lvl[3] = 0x00; in pll_calculate()
365 cfg->tx_lx_pre_driver_1[0] = 0x00; in pll_calculate()
366 cfg->tx_lx_pre_driver_1[1] = 0x00; in pll_calculate()
367 cfg->tx_lx_pre_driver_1[2] = 0x00; in pll_calculate()
368 cfg->tx_lx_pre_driver_1[3] = 0x00; in pll_calculate()
369 cfg->tx_lx_pre_driver_2[0] = 0x1C; in pll_calculate()
370 cfg->tx_lx_pre_driver_2[1] = 0x1C; in pll_calculate()
371 cfg->tx_lx_pre_driver_2[2] = 0x1C; in pll_calculate()
372 cfg->tx_lx_pre_driver_2[3] = 0x00; in pll_calculate()
373 cfg->tx_lx_res_code_offset[0] = 0x03; in pll_calculate()
374 cfg->tx_lx_res_code_offset[1] = 0x00; in pll_calculate()
375 cfg->tx_lx_res_code_offset[2] = 0x00; in pll_calculate()
376 cfg->tx_lx_res_code_offset[3] = 0x03; in pll_calculate()
378 cfg->tx_lx_tx_drv_lvl[0] = 0x0f; in pll_calculate()
379 cfg->tx_lx_tx_drv_lvl[1] = 0x0f; in pll_calculate()
380 cfg->tx_lx_tx_drv_lvl[2] = 0x0f; in pll_calculate()
381 cfg->tx_lx_tx_drv_lvl[3] = 0x0f; in pll_calculate()
382 cfg->tx_lx_tx_emp_post1_lvl[0] = 0x03; in pll_calculate()
383 cfg->tx_lx_tx_emp_post1_lvl[1] = 0x03; in pll_calculate()
384 cfg->tx_lx_tx_emp_post1_lvl[2] = 0x03; in pll_calculate()
385 cfg->tx_lx_tx_emp_post1_lvl[3] = 0x00; in pll_calculate()
386 cfg->tx_lx_pre_driver_1[0] = 0x00; in pll_calculate()
387 cfg->tx_lx_pre_driver_1[1] = 0x00; in pll_calculate()
388 cfg->tx_lx_pre_driver_1[2] = 0x00; in pll_calculate()
389 cfg->tx_lx_pre_driver_1[3] = 0x00; in pll_calculate()
390 cfg->tx_lx_pre_driver_2[0] = 0x16; in pll_calculate()
391 cfg->tx_lx_pre_driver_2[1] = 0x16; in pll_calculate()
392 cfg->tx_lx_pre_driver_2[2] = 0x16; in pll_calculate()
393 cfg->tx_lx_pre_driver_2[3] = 0x18; in pll_calculate()
394 cfg->tx_lx_res_code_offset[0] = 0x03; in pll_calculate()
395 cfg->tx_lx_res_code_offset[1] = 0x00; in pll_calculate()
396 cfg->tx_lx_res_code_offset[2] = 0x00; in pll_calculate()
397 cfg->tx_lx_res_code_offset[3] = 0x00; in pll_calculate()
399 cfg->tx_lx_tx_drv_lvl[0] = 0x0f; in pll_calculate()
400 cfg->tx_lx_tx_drv_lvl[1] = 0x0f; in pll_calculate()
401 cfg->tx_lx_tx_drv_lvl[2] = 0x0f; in pll_calculate()
402 cfg->tx_lx_tx_drv_lvl[3] = 0x0f; in pll_calculate()
403 cfg->tx_lx_tx_emp_post1_lvl[0] = 0x05; in pll_calculate()
404 cfg->tx_lx_tx_emp_post1_lvl[1] = 0x05; in pll_calculate()
405 cfg->tx_lx_tx_emp_post1_lvl[2] = 0x05; in pll_calculate()
406 cfg->tx_lx_tx_emp_post1_lvl[3] = 0x00; in pll_calculate()
407 cfg->tx_lx_pre_driver_1[0] = 0x00; in pll_calculate()
408 cfg->tx_lx_pre_driver_1[1] = 0x00; in pll_calculate()
409 cfg->tx_lx_pre_driver_1[2] = 0x00; in pll_calculate()
410 cfg->tx_lx_pre_driver_1[3] = 0x00; in pll_calculate()
411 cfg->tx_lx_pre_driver_2[0] = 0x0E; in pll_calculate()
412 cfg->tx_lx_pre_driver_2[1] = 0x0E; in pll_calculate()
413 cfg->tx_lx_pre_driver_2[2] = 0x0E; in pll_calculate()
414 cfg->tx_lx_pre_driver_2[3] = 0x0E; in pll_calculate()
415 cfg->tx_lx_res_code_offset[0] = 0x00; in pll_calculate()
416 cfg->tx_lx_res_code_offset[1] = 0x00; in pll_calculate()
417 cfg->tx_lx_res_code_offset[2] = 0x00; in pll_calculate()
418 cfg->tx_lx_res_code_offset[3] = 0x00; in pll_calculate()
420 cfg->tx_lx_tx_drv_lvl[0] = 0x01; in pll_calculate()
421 cfg->tx_lx_tx_drv_lvl[1] = 0x01; in pll_calculate()
422 cfg->tx_lx_tx_drv_lvl[2] = 0x01; in pll_calculate()
423 cfg->tx_lx_tx_drv_lvl[3] = 0x00; in pll_calculate()
424 cfg->tx_lx_tx_emp_post1_lvl[0] = 0x00; in pll_calculate()
425 cfg->tx_lx_tx_emp_post1_lvl[1] = 0x00; in pll_calculate()
426 cfg->tx_lx_tx_emp_post1_lvl[2] = 0x00; in pll_calculate()
427 cfg->tx_lx_tx_emp_post1_lvl[3] = 0x00; in pll_calculate()
428 cfg->tx_lx_pre_driver_1[0] = 0x00; in pll_calculate()
429 cfg->tx_lx_pre_driver_1[1] = 0x00; in pll_calculate()
430 cfg->tx_lx_pre_driver_1[2] = 0x00; in pll_calculate()
431 cfg->tx_lx_pre_driver_1[3] = 0x00; in pll_calculate()
432 cfg->tx_lx_pre_driver_2[0] = 0x16; in pll_calculate()
433 cfg->tx_lx_pre_driver_2[1] = 0x16; in pll_calculate()
434 cfg->tx_lx_pre_driver_2[2] = 0x16; in pll_calculate()
435 cfg->tx_lx_pre_driver_2[3] = 0x18; in pll_calculate()
436 cfg->tx_lx_res_code_offset[0] = 0x00; in pll_calculate()
437 cfg->tx_lx_res_code_offset[1] = 0x00; in pll_calculate()
438 cfg->tx_lx_res_code_offset[2] = 0x00; in pll_calculate()
439 cfg->tx_lx_res_code_offset[3] = 0x00; in pll_calculate()
442 return 0; in pll_calculate()
448 struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw); in hdmi_8998_pll_set_clk_rate() local
449 struct hdmi_phy *phy = pll_get_phy(pll); in hdmi_8998_pll_set_clk_rate()
455 DRM_ERROR("PLL calculation failed\n"); in hdmi_8998_pll_set_clk_rate()
460 hdmi_phy_write(phy, REG_HDMI_8998_PHY_PD_CTL, 0x0); in hdmi_8998_pll_set_clk_rate()
464 hdmi_phy_write(phy, REG_HDMI_8998_PHY_PD_CTL, 0x1); in hdmi_8998_pll_set_clk_rate()
465 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_RESETSM_CNTRL, 0x20); in hdmi_8998_pll_set_clk_rate()
466 hdmi_phy_write(phy, REG_HDMI_8998_PHY_CMN_CTRL, 0x6); in hdmi_8998_pll_set_clk_rate()
468 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) { in hdmi_8998_pll_set_clk_rate()
469 hdmi_tx_chan_write(pll, i, in hdmi_8998_pll_set_clk_rate()
472 hdmi_tx_chan_write(pll, i, in hdmi_8998_pll_set_clk_rate()
474 0x1); in hdmi_8998_pll_set_clk_rate()
475 hdmi_tx_chan_write(pll, i, in hdmi_8998_pll_set_clk_rate()
477 0x20); in hdmi_8998_pll_set_clk_rate()
480 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE, 0x02); in hdmi_8998_pll_set_clk_rate()
481 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x0B); in hdmi_8998_pll_set_clk_rate()
482 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_SYSCLK_EN_SEL, 0x37); in hdmi_8998_pll_set_clk_rate()
483 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_SYS_CLK_CTRL, 0x02); in hdmi_8998_pll_set_clk_rate()
484 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CLK_ENABLE1, 0x0E); in hdmi_8998_pll_set_clk_rate()
487 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_SVS_MODE_CLK_SEL, in hdmi_8998_pll_set_clk_rate()
490 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_PLL_IVCO, 0x07); in hdmi_8998_pll_set_clk_rate()
491 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_VCO_TUNE_CTRL, 0x00); in hdmi_8998_pll_set_clk_rate()
493 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CLK_SEL, 0x30); in hdmi_8998_pll_set_clk_rate()
494 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_HSCLK_SEL, in hdmi_8998_pll_set_clk_rate()
496 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP_EN, in hdmi_8998_pll_set_clk_rate()
499 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_PLL_CCTRL_MODE0, in hdmi_8998_pll_set_clk_rate()
501 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_PLL_RCTRL_MODE0, in hdmi_8998_pll_set_clk_rate()
503 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CP_CTRL_MODE0, in hdmi_8998_pll_set_clk_rate()
505 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_DEC_START_MODE0, in hdmi_8998_pll_set_clk_rate()
507 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0, in hdmi_8998_pll_set_clk_rate()
509 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0, in hdmi_8998_pll_set_clk_rate()
511 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0, in hdmi_8998_pll_set_clk_rate()
514 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0, in hdmi_8998_pll_set_clk_rate()
516 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0, in hdmi_8998_pll_set_clk_rate()
519 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP1_MODE0, in hdmi_8998_pll_set_clk_rate()
521 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP2_MODE0, in hdmi_8998_pll_set_clk_rate()
523 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP3_MODE0, in hdmi_8998_pll_set_clk_rate()
526 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_VCO_TUNE_MAP, 0x00); in hdmi_8998_pll_set_clk_rate()
527 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CORE_CLK_EN, in hdmi_8998_pll_set_clk_rate()
529 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CORECLK_DIV_MODE0, in hdmi_8998_pll_set_clk_rate()
532 /* TX lanes setup (TX 0/1/2/3) */ in hdmi_8998_pll_set_clk_rate()
533 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) { in hdmi_8998_pll_set_clk_rate()
534 hdmi_tx_chan_write(pll, i, in hdmi_8998_pll_set_clk_rate()
537 hdmi_tx_chan_write(pll, i, in hdmi_8998_pll_set_clk_rate()
540 hdmi_tx_chan_write(pll, i, in hdmi_8998_pll_set_clk_rate()
543 hdmi_tx_chan_write(pll, i, in hdmi_8998_pll_set_clk_rate()
546 hdmi_tx_chan_write(pll, i, in hdmi_8998_pll_set_clk_rate()
553 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) { in hdmi_8998_pll_set_clk_rate()
554 hdmi_tx_chan_write(pll, i, in hdmi_8998_pll_set_clk_rate()
556 0x10); in hdmi_8998_pll_set_clk_rate()
561 * enabling the PLL in hdmi_8998_pll_set_clk_rate()
565 pll->rate = rate; in hdmi_8998_pll_set_clk_rate()
567 return 0; in hdmi_8998_pll_set_clk_rate()
575 int phy_ready = 0; in hdmi_8998_phy_ready_status()
577 while (nb_tries--) { in hdmi_8998_phy_ready_status()
579 phy_ready = status & BIT(0); in hdmi_8998_phy_ready_status()
590 static int hdmi_8998_pll_lock_status(struct hdmi_pll_8998 *pll) in hdmi_8998_pll_lock_status() argument
595 int pll_locked = 0; in hdmi_8998_pll_lock_status()
597 while (nb_tries--) { in hdmi_8998_pll_lock_status()
598 status = hdmi_pll_read(pll, in hdmi_8998_pll_lock_status()
600 pll_locked = status & BIT(0); in hdmi_8998_pll_lock_status()
613 struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw); in hdmi_8998_pll_prepare() local
614 struct hdmi_phy *phy = pll_get_phy(pll); in hdmi_8998_pll_prepare()
615 int i, ret = 0; in hdmi_8998_pll_prepare()
617 hdmi_phy_write(phy, REG_HDMI_8998_PHY_CFG, 0x1); in hdmi_8998_pll_prepare()
620 hdmi_phy_write(phy, REG_HDMI_8998_PHY_CFG, 0x59); in hdmi_8998_pll_prepare()
623 ret = hdmi_8998_pll_lock_status(pll); in hdmi_8998_pll_prepare()
627 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) { in hdmi_8998_pll_prepare()
628 hdmi_tx_chan_write(pll, i, in hdmi_8998_pll_prepare()
629 REG_HDMI_8998_PHY_TXn_LANE_CONFIG, 0x1F); in hdmi_8998_pll_prepare()
640 hdmi_phy_write(phy, REG_HDMI_8998_PHY_CFG, 0x58); in hdmi_8998_pll_prepare()
642 hdmi_phy_write(phy, REG_HDMI_8998_PHY_CFG, 0x59); in hdmi_8998_pll_prepare()
647 return 0; in hdmi_8998_pll_prepare()
665 struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw); in hdmi_8998_pll_recalc_rate() local
666 return pll->rate; in hdmi_8998_pll_recalc_rate()
671 struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw); in hdmi_8998_pll_unprepare() local
672 struct hdmi_phy *phy = pll_get_phy(pll); in hdmi_8998_pll_unprepare()
674 hdmi_phy_write(phy, REG_HDMI_8998_PHY_PD_CTL, 0); in hdmi_8998_pll_unprepare()
680 struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw); in hdmi_8998_pll_is_enabled() local
684 status = hdmi_pll_read(pll, REG_HDMI_8998_PHY_QSERDES_COM_C_READY_STATUS); in hdmi_8998_pll_is_enabled()
685 pll_locked = status & BIT(0); in hdmi_8998_pll_is_enabled()
711 struct device *dev = &pdev->dev; in msm_hdmi_pll_8998_init()
712 struct hdmi_pll_8998 *pll; in msm_hdmi_pll_8998_init() local
715 pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); in msm_hdmi_pll_8998_init()
716 if (!pll) in msm_hdmi_pll_8998_init()
717 return -ENOMEM; in msm_hdmi_pll_8998_init()
719 pll->pdev = pdev; in msm_hdmi_pll_8998_init()
721 pll->mmio_qserdes_com = msm_ioremap(pdev, "hdmi_pll"); in msm_hdmi_pll_8998_init()
722 if (IS_ERR(pll->mmio_qserdes_com)) { in msm_hdmi_pll_8998_init()
723 DRM_DEV_ERROR(dev, "failed to map pll base\n"); in msm_hdmi_pll_8998_init()
724 return -ENOMEM; in msm_hdmi_pll_8998_init()
727 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) { in msm_hdmi_pll_8998_init()
732 pll->mmio_qserdes_tx[i] = msm_ioremap(pdev, name); in msm_hdmi_pll_8998_init()
733 if (IS_ERR(pll->mmio_qserdes_tx[i])) { in msm_hdmi_pll_8998_init()
734 DRM_DEV_ERROR(dev, "failed to map pll base\n"); in msm_hdmi_pll_8998_init()
735 return -ENOMEM; in msm_hdmi_pll_8998_init()
738 pll->clk_hw.init = &pll_init; in msm_hdmi_pll_8998_init()
740 ret = devm_clk_hw_register(dev, &pll->clk_hw); in msm_hdmi_pll_8998_init()
742 DRM_DEV_ERROR(dev, "failed to register pll clock\n"); in msm_hdmi_pll_8998_init()
746 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &pll->clk_hw); in msm_hdmi_pll_8998_init()
752 return 0; in msm_hdmi_pll_8998_init()