Lines Matching +full:pll +full:- +full:0
1 // SPDX-License-Identifier: MIT
25 for ((__lane) = 0; (__lane) < 2; (__lane)++) \
28 #define INTEL_CX0_LANE0 BIT(0)
34 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_encoder_is_c10phy()
47 return 0; in lane_mask_to_lane()
60 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
73 drm_WARN_ON(&i915->drm, !enabled); in assert_dc_off()
79 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_program_msgbus_timer()
83 XELPDP_PORT_MSGBUS_TIMER(i915, encoder->port, lane), in intel_cx0_program_msgbus_timer()
100 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_begin()
112 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_end()
122 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_clear_response_ready_flag()
124 intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, encoder->port, lane), in intel_clear_response_ready_flag()
125 0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET); in intel_clear_response_ready_flag()
130 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_bus_reset()
131 enum port port = encoder->port; in intel_cx0_bus_reset()
140 drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy)); in intel_cx0_bus_reset()
150 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_wait_for_ack()
151 enum port port = encoder->port; in intel_cx0_wait_for_ack()
160 drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", in intel_cx0_wait_for_ack()
165 drm_dbg_kms(&i915->drm, in intel_cx0_wait_for_ack()
170 return -ETIMEDOUT; in intel_cx0_wait_for_ack()
174 drm_dbg_kms(&i915->drm, "PHY %c Error occurred during %s command. Status: 0x%x\n", phy_name(phy), in intel_cx0_wait_for_ack()
177 return -EINVAL; in intel_cx0_wait_for_ack()
181 drm_dbg_kms(&i915->drm, "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", phy_name(phy), in intel_cx0_wait_for_ack()
184 return -EINVAL; in intel_cx0_wait_for_ack()
187 return 0; in intel_cx0_wait_for_ack()
193 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in __intel_cx0_read_once()
194 enum port port = encoder->port; in __intel_cx0_read_once()
202 drm_dbg_kms(&i915->drm, in __intel_cx0_read_once()
205 return -ETIMEDOUT; in __intel_cx0_read_once()
214 if (ack < 0) in __intel_cx0_read_once()
232 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in __intel_cx0_read()
239 for (i = 0; i < 3; i++) { in __intel_cx0_read()
242 if (status >= 0) in __intel_cx0_read()
246 drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n", in __intel_cx0_read()
249 return 0; in __intel_cx0_read()
263 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in __intel_cx0_write_once()
264 enum port port = encoder->port; in __intel_cx0_write_once()
272 drm_dbg_kms(&i915->drm, in __intel_cx0_write_once()
275 return -ETIMEDOUT; in __intel_cx0_write_once()
288 drm_dbg_kms(&i915->drm, in __intel_cx0_write_once()
291 return -ETIMEDOUT; in __intel_cx0_write_once()
296 if (ack < 0) in __intel_cx0_write_once()
300 drm_dbg_kms(&i915->drm, in __intel_cx0_write_once()
303 return -EINVAL; in __intel_cx0_write_once()
315 return 0; in __intel_cx0_write_once()
321 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in __intel_cx0_write()
328 for (i = 0; i < 3; i++) { in __intel_cx0_write()
331 if (status == 0) in __intel_cx0_write()
335 drm_err_once(&i915->drm, in __intel_cx0_write()
351 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_c20_sram_write()
355 intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0); in intel_c20_sram_write()
356 intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0); in intel_c20_sram_write()
358 intel_cx0_write(encoder, lane, PHY_C20_WR_DATA_H, data >> 8, 0); in intel_c20_sram_write()
359 intel_cx0_write(encoder, lane, PHY_C20_WR_DATA_L, data & 0xff, 1); in intel_c20_sram_write()
365 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_c20_sram_read()
370 intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0); in intel_c20_sram_read()
371 intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1); in intel_c20_sram_read()
405 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_vboost_lvl()
406 crtc_state->port_clock == 810000)) in intel_c10_get_tx_vboost_lvl()
419 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_term_ctl()
420 crtc_state->port_clock == 810000)) in intel_c10_get_tx_term_ctl()
432 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_set_signal_levels()
446 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in intel_cx0_phy_set_signal_levels()
447 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) { in intel_cx0_phy_set_signal_levels()
454 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); in intel_cx0_phy_set_signal_levels()
465 for (ln = 0; ln < crtc_state->lane_count; ln++) { in intel_cx0_phy_set_signal_levels()
469 u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; in intel_cx0_phy_set_signal_levels()
474 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 0), in intel_cx0_phy_set_signal_levels()
476 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor), in intel_cx0_phy_set_signal_levels()
480 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing), in intel_cx0_phy_set_signal_levels()
484 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor), in intel_cx0_phy_set_signal_levels()
488 /* Write Override enables in 0xD71 */ in intel_cx0_phy_set_signal_levels()
490 0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2, in intel_cx0_phy_set_signal_levels()
495 0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED); in intel_cx0_phy_set_signal_levels()
502 * Note: The tables below are with SSC. In non-ssc
503 * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be
504 * programmed 0.
509 .tx = 0x10,
510 .cmn = 0x21,
511 .pll[0] = 0xB4,
512 .pll[1] = 0,
513 .pll[2] = 0x30,
514 .pll[3] = 0x1,
515 .pll[4] = 0x26,
516 .pll[5] = 0x0C,
517 .pll[6] = 0x98,
518 .pll[7] = 0x46,
519 .pll[8] = 0x1,
520 .pll[9] = 0x1,
521 .pll[10] = 0,
522 .pll[11] = 0,
523 .pll[12] = 0xC0,
524 .pll[13] = 0,
525 .pll[14] = 0,
526 .pll[15] = 0x2,
527 .pll[16] = 0x84,
528 .pll[17] = 0x4F,
529 .pll[18] = 0xE5,
530 .pll[19] = 0x23,
535 .tx = 0x10,
536 .cmn = 0x21,
537 .pll[0] = 0x4,
538 .pll[1] = 0,
539 .pll[2] = 0xA2,
540 .pll[3] = 0x1,
541 .pll[4] = 0x33,
542 .pll[5] = 0x10,
543 .pll[6] = 0x75,
544 .pll[7] = 0xB3,
545 .pll[8] = 0x1,
546 .pll[9] = 0x1,
547 .pll[10] = 0,
548 .pll[11] = 0,
549 .pll[12] = 0,
550 .pll[13] = 0,
551 .pll[14] = 0,
552 .pll[15] = 0x2,
553 .pll[16] = 0x85,
554 .pll[17] = 0x0F,
555 .pll[18] = 0xE6,
556 .pll[19] = 0x23,
561 .tx = 0x10,
562 .cmn = 0x21,
563 .pll[0] = 0x34,
564 .pll[1] = 0,
565 .pll[2] = 0xDA,
566 .pll[3] = 0x1,
567 .pll[4] = 0x39,
568 .pll[5] = 0x12,
569 .pll[6] = 0xE3,
570 .pll[7] = 0xE9,
571 .pll[8] = 0x1,
572 .pll[9] = 0x1,
573 .pll[10] = 0,
574 .pll[11] = 0,
575 .pll[12] = 0x20,
576 .pll[13] = 0,
577 .pll[14] = 0,
578 .pll[15] = 0x2,
579 .pll[16] = 0x85,
580 .pll[17] = 0x8F,
581 .pll[18] = 0xE6,
582 .pll[19] = 0x23,
587 .tx = 0x10,
588 .cmn = 0x21,
589 .pll[0] = 0xF4,
590 .pll[1] = 0,
591 .pll[2] = 0xF8,
592 .pll[3] = 0x0,
593 .pll[4] = 0x20,
594 .pll[5] = 0x0A,
595 .pll[6] = 0x29,
596 .pll[7] = 0x10,
597 .pll[8] = 0x1, /* Verify */
598 .pll[9] = 0x1,
599 .pll[10] = 0,
600 .pll[11] = 0,
601 .pll[12] = 0xA0,
602 .pll[13] = 0,
603 .pll[14] = 0,
604 .pll[15] = 0x1,
605 .pll[16] = 0x84,
606 .pll[17] = 0x4F,
607 .pll[18] = 0xE5,
608 .pll[19] = 0x23,
613 .tx = 0x10,
614 .cmn = 0x21,
615 .pll[0] = 0xB4,
616 .pll[1] = 0,
617 .pll[2] = 0x30,
618 .pll[3] = 0x1,
619 .pll[4] = 0x26,
620 .pll[5] = 0x0C,
621 .pll[6] = 0x98,
622 .pll[7] = 0x46,
623 .pll[8] = 0x1,
624 .pll[9] = 0x1,
625 .pll[10] = 0,
626 .pll[11] = 0,
627 .pll[12] = 0xC0,
628 .pll[13] = 0,
629 .pll[14] = 0,
630 .pll[15] = 0x1,
631 .pll[16] = 0x85,
632 .pll[17] = 0x4F,
633 .pll[18] = 0xE6,
634 .pll[19] = 0x23,
639 .tx = 0x10,
640 .cmn = 0x21,
641 .pll[0] = 0x4,
642 .pll[1] = 0,
643 .pll[2] = 0xA2,
644 .pll[3] = 0x1,
645 .pll[4] = 0x33,
646 .pll[5] = 0x10,
647 .pll[6] = 0x75,
648 .pll[7] = 0xB3,
649 .pll[8] = 0x1,
650 .pll[9] = 0x1,
651 .pll[10] = 0,
652 .pll[11] = 0,
653 .pll[12] = 0,
654 .pll[13] = 0,
655 .pll[14] = 0,
656 .pll[15] = 0x1,
657 .pll[16] = 0x85,
658 .pll[17] = 0x0F,
659 .pll[18] = 0xE6,
660 .pll[19] = 0x23,
665 .tx = 0x10,
666 .cmn = 0x21,
667 .pll[0] = 0xF4,
668 .pll[1] = 0,
669 .pll[2] = 0xF8,
670 .pll[3] = 0,
671 .pll[4] = 0x20,
672 .pll[5] = 0x0A,
673 .pll[6] = 0x29,
674 .pll[7] = 0x10,
675 .pll[8] = 0x1,
676 .pll[9] = 0x1,
677 .pll[10] = 0,
678 .pll[11] = 0,
679 .pll[12] = 0xA0,
680 .pll[13] = 0,
681 .pll[14] = 0,
682 .pll[15] = 0,
683 .pll[16] = 0x84,
684 .pll[17] = 0x4F,
685 .pll[18] = 0xE5,
686 .pll[19] = 0x23,
691 .tx = 0x10,
692 .cmn = 0x21,
693 .pll[0] = 0xB4,
694 .pll[1] = 0,
695 .pll[2] = 0x3E,
696 .pll[3] = 0x1,
697 .pll[4] = 0xA8,
698 .pll[5] = 0x0C,
699 .pll[6] = 0x33,
700 .pll[7] = 0x54,
701 .pll[8] = 0x1,
702 .pll[9] = 0x1,
703 .pll[10] = 0,
704 .pll[11] = 0,
705 .pll[12] = 0xC8,
706 .pll[13] = 0,
707 .pll[14] = 0,
708 .pll[15] = 0,
709 .pll[16] = 0x85,
710 .pll[17] = 0x8F,
711 .pll[18] = 0xE6,
712 .pll[19] = 0x23,
717 .tx = 0x10,
718 .cmn = 0x21,
719 .pll[0] = 0x34,
720 .pll[1] = 0,
721 .pll[2] = 0x84,
722 .pll[3] = 0x1,
723 .pll[4] = 0x30,
724 .pll[5] = 0x0F,
725 .pll[6] = 0x3D,
726 .pll[7] = 0x98,
727 .pll[8] = 0x1,
728 .pll[9] = 0x1,
729 .pll[10] = 0,
730 .pll[11] = 0,
731 .pll[12] = 0xF0,
732 .pll[13] = 0,
733 .pll[14] = 0,
734 .pll[15] = 0,
735 .pll[16] = 0x84,
736 .pll[17] = 0x0F,
737 .pll[18] = 0xE5,
738 .pll[19] = 0x23,
765 .tx = { 0xbe88, /* tx cfg0 */
766 0x5800, /* tx cfg1 */
767 0x0000, /* tx cfg2 */
769 .cmn = {0x0500, /* cmn cfg0*/
770 0x0005, /* cmn cfg1 */
771 0x0000, /* cmn cfg2 */
772 0x0000, /* cmn cfg3 */
774 .mpllb = { 0x50a8, /* mpllb cfg0 */
775 0x2120, /* mpllb cfg1 */
776 0xcd9a, /* mpllb cfg2 */
777 0xbfc1, /* mpllb cfg3 */
778 0x5ab8, /* mpllb cfg4 */
779 0x4c34, /* mpllb cfg5 */
780 0x2000, /* mpllb cfg6 */
781 0x0001, /* mpllb cfg7 */
782 0x6000, /* mpllb cfg8 */
783 0x0000, /* mpllb cfg9 */
784 0x0000, /* mpllb cfg10 */
790 .tx = { 0xbe88, /* tx cfg0 */
791 0x4800, /* tx cfg1 */
792 0x0000, /* tx cfg2 */
794 .cmn = {0x0500, /* cmn cfg0*/
795 0x0005, /* cmn cfg1 */
796 0x0000, /* cmn cfg2 */
797 0x0000, /* cmn cfg3 */
799 .mpllb = { 0x308c, /* mpllb cfg0 */
800 0x2110, /* mpllb cfg1 */
801 0xcc9c, /* mpllb cfg2 */
802 0xbfc1, /* mpllb cfg3 */
803 0x4b9a, /* mpllb cfg4 */
804 0x3f81, /* mpllb cfg5 */
805 0x2000, /* mpllb cfg6 */
806 0x0001, /* mpllb cfg7 */
807 0x5000, /* mpllb cfg8 */
808 0x0000, /* mpllb cfg9 */
809 0x0000, /* mpllb cfg10 */
815 .tx = { 0xbe88, /* tx cfg0 */
816 0x4800, /* tx cfg1 */
817 0x0000, /* tx cfg2 */
819 .cmn = {0x0500, /* cmn cfg0*/
820 0x0005, /* cmn cfg1 */
821 0x0000, /* cmn cfg2 */
822 0x0000, /* cmn cfg3 */
824 .mpllb = { 0x108c, /* mpllb cfg0 */
825 0x2108, /* mpllb cfg1 */
826 0xcc9c, /* mpllb cfg2 */
827 0xbfc1, /* mpllb cfg3 */
828 0x4b9a, /* mpllb cfg4 */
829 0x3f81, /* mpllb cfg5 */
830 0x2000, /* mpllb cfg6 */
831 0x0001, /* mpllb cfg7 */
832 0x5000, /* mpllb cfg8 */
833 0x0000, /* mpllb cfg9 */
834 0x0000, /* mpllb cfg10 */
840 .tx = { 0xbe88, /* tx cfg0 */
841 0x4800, /* tx cfg1 */
842 0x0000, /* tx cfg2 */
844 .cmn = {0x0500, /* cmn cfg0*/
845 0x0005, /* cmn cfg1 */
846 0x0000, /* cmn cfg2 */
847 0x0000, /* cmn cfg3 */
849 .mpllb = { 0x10d2, /* mpllb cfg0 */
850 0x2108, /* mpllb cfg1 */
851 0x8d98, /* mpllb cfg2 */
852 0xbfc1, /* mpllb cfg3 */
853 0x7166, /* mpllb cfg4 */
854 0x5f42, /* mpllb cfg5 */
855 0x2000, /* mpllb cfg6 */
856 0x0001, /* mpllb cfg7 */
857 0x7800, /* mpllb cfg8 */
858 0x0000, /* mpllb cfg9 */
859 0x0000, /* mpllb cfg10 */
866 .tx = { 0xbe21, /* tx cfg0 */
867 0xe800, /* tx cfg1 */
868 0x0000, /* tx cfg2 */
870 .cmn = {0x0700, /* cmn cfg0*/
871 0x0005, /* cmn cfg1 */
872 0x0000, /* cmn cfg2 */
873 0x0000, /* cmn cfg3 */
875 .mplla = { 0x3104, /* mplla cfg0 */
876 0xd105, /* mplla cfg1 */
877 0xc025, /* mplla cfg2 */
878 0xc025, /* mplla cfg3 */
879 0x8c00, /* mplla cfg4 */
880 0x759a, /* mplla cfg5 */
881 0x4000, /* mplla cfg6 */
882 0x0003, /* mplla cfg7 */
883 0x3555, /* mplla cfg8 */
884 0x0001, /* mplla cfg9 */
890 .tx = { 0xbea0, /* tx cfg0 */
891 0x4800, /* tx cfg1 */
892 0x0000, /* tx cfg2 */
894 .cmn = {0x0500, /* cmn cfg0*/
895 0x0005, /* cmn cfg1 */
896 0x0000, /* cmn cfg2 */
897 0x0000, /* cmn cfg3 */
899 .mpllb = { 0x015f, /* mpllb cfg0 */
900 0x2205, /* mpllb cfg1 */
901 0x1b17, /* mpllb cfg2 */
902 0xffc1, /* mpllb cfg3 */
903 0xe100, /* mpllb cfg4 */
904 0xbd00, /* mpllb cfg5 */
905 0x2000, /* mpllb cfg6 */
906 0x0001, /* mpllb cfg7 */
907 0x4800, /* mpllb cfg8 */
908 0x0000, /* mpllb cfg9 */
909 0x0000, /* mpllb cfg10 */
915 .tx = { 0xbe20, /* tx cfg0 */
916 0x4800, /* tx cfg1 */
917 0x0000, /* tx cfg2 */
919 .cmn = {0x0500, /* cmn cfg0*/
920 0x0005, /* cmn cfg1 */
921 0x0000, /* cmn cfg2 */
922 0x0000, /* cmn cfg3 */
924 .mplla = { 0x3104, /* mplla cfg0 */
925 0xd105, /* mplla cfg1 */
926 0xc025, /* mplla cfg2 */
927 0xc025, /* mplla cfg3 */
928 0xa6ab, /* mplla cfg4 */
929 0x8c00, /* mplla cfg5 */
930 0x4000, /* mplla cfg6 */
931 0x0003, /* mplla cfg7 */
932 0x3555, /* mplla cfg8 */
933 0x0001, /* mplla cfg9 */
954 .tx = { 0xbe88,
955 0x4800,
956 0x0000,
958 .cmn = { 0x0500,
959 0x0005,
960 0x0000,
961 0x0000,
963 .mpllb = { 0x50e1,
964 0x2120,
965 0x8e18,
966 0xbfc1,
967 0x9000,
968 0x78f6,
969 0x0000,
970 0x0000,
971 0x0000,
972 0x0000,
973 0x0000,
979 .tx = { 0xbe88,
980 0x4800,
981 0x0000,
983 .cmn = { 0x0500,
984 0x0005,
985 0x0000,
986 0x0000,
988 .mpllb = { 0x50fd,
989 0x2120,
990 0x8f18,
991 0xbfc1,
992 0xa200,
993 0x8814,
994 0x2000,
995 0x0001,
996 0x1000,
997 0x0000,
998 0x0000,
1004 .tx = { 0xbe88,
1005 0x4800,
1006 0x0000,
1008 .cmn = { 0x0500,
1009 0x0005,
1010 0x0000,
1011 0x0000,
1013 .mpllb = { 0x30a8,
1014 0x2110,
1015 0xcd9a,
1016 0xbfc1,
1017 0x6c00,
1018 0x5ab8,
1019 0x2000,
1020 0x0001,
1021 0x6000,
1022 0x0000,
1023 0x0000,
1029 .tx = { 0xbe88,
1030 0x4800,
1031 0x0000,
1033 .cmn = { 0x0500,
1034 0x0005,
1035 0x0000,
1036 0x0000,
1038 .mpllb = { 0x30e1,
1039 0x2110,
1040 0x8e18,
1041 0xbfc1,
1042 0x9000,
1043 0x78f6,
1044 0x0000,
1045 0x0000,
1046 0x0000,
1047 0x0000,
1048 0x0000,
1054 .tx = { 0xbe88,
1055 0x4800,
1056 0x0000,
1058 .cmn = { 0x0500,
1059 0x0005,
1060 0x0000,
1061 0x0000,
1063 .mpllb = { 0x10af,
1064 0x2108,
1065 0xce1a,
1066 0xbfc1,
1067 0x7080,
1068 0x5e80,
1069 0x2000,
1070 0x0001,
1071 0x6400,
1072 0x0000,
1073 0x0000,
1092 .tx = { 0xbea0, /* tx cfg0 */
1093 0x4800, /* tx cfg1 */
1094 0x0000, /* tx cfg2 */
1096 .cmn = {0x0500, /* cmn cfg0*/
1097 0x0005, /* cmn cfg1 */
1098 0x0000, /* cmn cfg2 */
1099 0x0000, /* cmn cfg3 */
1101 .mpllb = { 0x015f, /* mpllb cfg0 */
1102 0x2205, /* mpllb cfg1 */
1103 0x1b17, /* mpllb cfg2 */
1104 0xffc1, /* mpllb cfg3 */
1105 0xbd00, /* mpllb cfg4 */
1106 0x9ec3, /* mpllb cfg5 */
1107 0x2000, /* mpllb cfg6 */
1108 0x0001, /* mpllb cfg7 */
1109 0x4800, /* mpllb cfg8 */
1110 0x0000, /* mpllb cfg9 */
1111 0x0000, /* mpllb cfg10 */
1131 .tx = 0x10,
1132 .cmn = 0x1,
1133 .pll[0] = 0x4,
1134 .pll[1] = 0,
1135 .pll[2] = 0xB2,
1136 .pll[3] = 0,
1137 .pll[4] = 0,
1138 .pll[5] = 0,
1139 .pll[6] = 0,
1140 .pll[7] = 0,
1141 .pll[8] = 0x20,
1142 .pll[9] = 0x1,
1143 .pll[10] = 0,
1144 .pll[11] = 0,
1145 .pll[12] = 0,
1146 .pll[13] = 0,
1147 .pll[14] = 0,
1148 .pll[15] = 0xD,
1149 .pll[16] = 0x6,
1150 .pll[17] = 0x8F,
1151 .pll[18] = 0x84,
1152 .pll[19] = 0x23,
1157 .tx = 0x10,
1158 .cmn = 0x1,
1159 .pll[0] = 0x34,
1160 .pll[1] = 0,
1161 .pll[2] = 0xC0,
1162 .pll[3] = 0,
1163 .pll[4] = 0,
1164 .pll[5] = 0,
1165 .pll[6] = 0,
1166 .pll[7] = 0,
1167 .pll[8] = 0x20,
1168 .pll[9] = 0x1,
1169 .pll[10] = 0,
1170 .pll[11] = 0,
1171 .pll[12] = 0x80,
1172 .pll[13] = 0,
1173 .pll[14] = 0,
1174 .pll[15] = 0xD,
1175 .pll[16] = 0x6,
1176 .pll[17] = 0xCF,
1177 .pll[18] = 0x84,
1178 .pll[19] = 0x23,
1183 .tx = 0x10,
1184 .cmn = 0x1,
1185 .pll[0] = 0xF4,
1186 .pll[1] = 0,
1187 .pll[2] = 0x7A,
1188 .pll[3] = 0,
1189 .pll[4] = 0,
1190 .pll[5] = 0,
1191 .pll[6] = 0,
1192 .pll[7] = 0,
1193 .pll[8] = 0x20,
1194 .pll[9] = 0x1,
1195 .pll[10] = 0,
1196 .pll[11] = 0,
1197 .pll[12] = 0x58,
1198 .pll[13] = 0,
1199 .pll[14] = 0,
1200 .pll[15] = 0xB,
1201 .pll[16] = 0x6,
1202 .pll[17] = 0xF,
1203 .pll[18] = 0x85,
1204 .pll[19] = 0x23,
1209 .tx = 0x10,
1210 .cmn = 0x1,
1211 .pll[0] = 0xF4,
1212 .pll[1] = 0,
1213 .pll[2] = 0x7A,
1214 .pll[3] = 0,
1215 .pll[4] = 0,
1216 .pll[5] = 0,
1217 .pll[6] = 0,
1218 .pll[7] = 0,
1219 .pll[8] = 0x20,
1220 .pll[9] = 0x1,
1221 .pll[10] = 0,
1222 .pll[11] = 0,
1223 .pll[12] = 0x58,
1224 .pll[13] = 0,
1225 .pll[14] = 0,
1226 .pll[15] = 0xA,
1227 .pll[16] = 0x6,
1228 .pll[17] = 0xF,
1229 .pll[18] = 0x85,
1230 .pll[19] = 0x23,
1235 .tx = 0x10,
1236 .cmn = 0x1,
1237 .pll[0] = 0xF4,
1238 .pll[1] = 0,
1239 .pll[2] = 0x7A,
1240 .pll[3] = 0,
1241 .pll[4] = 0,
1242 .pll[5] = 0,
1243 .pll[6] = 0,
1244 .pll[7] = 0,
1245 .pll[8] = 0x20,
1246 .pll[9] = 0x1,
1247 .pll[10] = 0,
1248 .pll[11] = 0,
1249 .pll[12] = 0x58,
1250 .pll[13] = 0,
1251 .pll[14] = 0,
1252 .pll[15] = 0x8,
1253 .pll[16] = 0x6,
1254 .pll[17] = 0xF,
1255 .pll[18] = 0x85,
1256 .pll[19] = 0x23,
1259 /* Precomputed C10 HDMI PLL tables */
1262 .tx = 0x10,
1263 .cmn = 0x1,
1264 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1265 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1266 .pll[10] = 0xFF, .pll[11] = 0xCC, .pll[12] = 0x9C, .pll[13] = 0xCB, .pll[14] = 0xCC,
1267 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1272 .tx = 0x10,
1273 .cmn = 0x1,
1274 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,
1275 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1276 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
1277 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1282 .tx = 0x10,
1283 .cmn = 0x1,
1284 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,
1285 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1286 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
1287 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1292 .tx = 0x10,
1293 .cmn = 0x1,
1294 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,
1295 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1296 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xA0, .pll[13] = 0x00, .pll[14] = 0x00,
1297 .pll[15] = 0x0C, .pll[16] = 0x09, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1302 .tx = 0x10,
1303 .cmn = 0x1,
1304 .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,
1305 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1306 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
1307 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1312 .tx = 0x10,
1313 .cmn = 0x1,
1314 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1315 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1316 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x55, .pll[13] = 0x55, .pll[14] = 0x55,
1317 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1322 .tx = 0x10,
1323 .cmn = 0x1,
1324 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1325 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1326 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
1327 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1332 .tx = 0x10,
1333 .cmn = 0x1,
1334 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,
1335 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1336 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x2A, .pll[13] = 0xA9, .pll[14] = 0xAA,
1337 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1342 .tx = 0x10,
1343 .cmn = 0x1,
1344 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,
1345 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1346 .pll[10] = 0xFF, .pll[11] = 0x77, .pll[12] = 0x57, .pll[13] = 0x77, .pll[14] = 0x77,
1347 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1352 .tx = 0x10,
1353 .cmn = 0x1,
1354 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1355 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1356 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xD5, .pll[13] = 0x55, .pll[14] = 0x55,
1357 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1362 .tx = 0x10,
1363 .cmn = 0x1,
1364 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,
1365 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1366 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xB5, .pll[13] = 0x55, .pll[14] = 0x55,
1367 .pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1372 .tx = 0x10,
1373 .cmn = 0x1,
1374 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,
1375 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1376 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55,
1377 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1382 .tx = 0x10,
1383 .cmn = 0x1,
1384 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1385 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1386 .pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44,
1387 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1392 .tx = 0x10,
1393 .cmn = 0x1,
1394 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,
1395 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1396 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
1397 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1402 .tx = 0x10,
1403 .cmn = 0x1,
1404 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,
1405 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1406 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x08, .pll[13] = 0x00, .pll[14] = 0x00,
1407 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1412 .tx = 0x10,
1413 .cmn = 0x1,
1414 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,
1415 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1416 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x10, .pll[13] = 0x00, .pll[14] = 0x00,
1417 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1422 .tx = 0x10,
1423 .cmn = 0x1,
1424 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,
1425 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1426 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x72, .pll[13] = 0xA9, .pll[14] = 0xAA,
1427 .pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1432 .tx = 0x10,
1433 .cmn = 0x1,
1434 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,
1435 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1436 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xF0, .pll[13] = 0x00, .pll[14] = 0x00,
1437 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1442 .tx = 0x10,
1443 .cmn = 0x1,
1444 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1445 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1446 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x80, .pll[13] = 0x00, .pll[14] = 0x00,
1447 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1452 .tx = 0x10,
1453 .cmn = 0x1,
1454 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1455 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1456 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00,
1457 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1462 .tx = 0x10,
1463 .cmn = 0x1,
1464 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,
1465 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1466 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55,
1467 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1472 .tx = 0x10,
1473 .cmn = 0x1,
1474 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,
1475 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1476 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00,
1477 .pll[15] = 0x0A, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1482 .tx = 0x10,
1483 .cmn = 0x1,
1484 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,
1485 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1486 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x22, .pll[13] = 0xA9, .pll[14] = 0xAA,
1487 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1492 .tx = 0x10,
1493 .cmn = 0x1,
1494 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,
1495 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1496 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xA5, .pll[13] = 0x55, .pll[14] = 0x55,
1497 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1502 .tx = 0x10,
1503 .cmn = 0x1,
1504 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1505 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1506 .pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44,
1507 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1512 .tx = 0x10,
1513 .cmn = 0x1,
1514 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,
1515 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1516 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x35, .pll[13] = 0x55, .pll[14] = 0x55,
1517 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1522 .tx = 0x10,
1523 .cmn = 0x1,
1524 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,
1525 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1526 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x60, .pll[13] = 0x00, .pll[14] = 0x00,
1527 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1532 .tx = 0x10,
1533 .cmn = 0x1,
1534 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,
1535 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1536 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0xFA, .pll[13] = 0xA9, .pll[14] = 0xAA,
1537 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1542 .tx = 0x10,
1543 .cmn = 0x1,
1544 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1545 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1546 .pll[10] = 0xFF, .pll[11] = 0x99, .pll[12] = 0x05, .pll[13] = 0x98, .pll[14] = 0x99,
1547 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1552 .tx = 0x10,
1553 .cmn = 0x1,
1554 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1555 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1556 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
1557 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1562 .tx = 0x10,
1563 .cmn = 0x1,
1564 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,
1565 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1566 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x45, .pll[13] = 0x55, .pll[14] = 0x55,
1567 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1572 .tx = 0x10,
1573 .cmn = 0x1,
1574 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,
1575 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1576 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xC8, .pll[13] = 0x00, .pll[14] = 0x00,
1577 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1582 .tx = 0x10,
1583 .cmn = 0x1,
1584 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,
1585 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1586 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x6C, .pll[13] = 0xA9, .pll[14] = 0xAA,
1587 .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1592 .tx = 0x10,
1593 .cmn = 0x1,
1594 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,
1595 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1596 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xEC, .pll[13] = 0x00, .pll[14] = 0x00,
1597 .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1602 .tx = 0x10,
1603 .cmn = 0x1,
1604 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1605 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1606 .pll[10] = 0xFF, .pll[11] = 0x33, .pll[12] = 0x44, .pll[13] = 0x33, .pll[14] = 0x33,
1607 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1612 .tx = 0x10,
1613 .cmn = 0x1,
1614 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1615 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1616 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x58, .pll[13] = 0x00, .pll[14] = 0x00,
1617 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1622 .tx = 0x10,
1623 .cmn = 0x1,
1624 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1625 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1626 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x44, .pll[13] = 0xA9, .pll[14] = 0xAA,
1627 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1632 .tx = 0x10,
1633 .cmn = 0x1,
1634 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,
1635 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1636 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x9F, .pll[13] = 0x55, .pll[14] = 0x55,
1637 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1642 .tx = 0x10,
1643 .cmn = 0x1,
1644 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1645 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1646 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x15, .pll[13] = 0x55, .pll[14] = 0x55,
1647 .pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1652 .tx = 0x10,
1653 .cmn = 0x1,
1654 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1655 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1656 .pll[10] = 0xFF, .pll[11] = 0x3B, .pll[12] = 0x44, .pll[13] = 0xBA, .pll[14] = 0xBB,
1657 .pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1711 .tx = { 0xbe88, /* tx cfg0 */
1712 0x9800, /* tx cfg1 */
1713 0x0000, /* tx cfg2 */
1715 .cmn = { 0x0500, /* cmn cfg0*/
1716 0x0005, /* cmn cfg1 */
1717 0x0000, /* cmn cfg2 */
1718 0x0000, /* cmn cfg3 */
1720 .mpllb = { 0xa0d2, /* mpllb cfg0 */
1721 0x7d80, /* mpllb cfg1 */
1722 0x0906, /* mpllb cfg2 */
1723 0xbe40, /* mpllb cfg3 */
1724 0x0000, /* mpllb cfg4 */
1725 0x0000, /* mpllb cfg5 */
1726 0x0200, /* mpllb cfg6 */
1727 0x0001, /* mpllb cfg7 */
1728 0x0000, /* mpllb cfg8 */
1729 0x0000, /* mpllb cfg9 */
1730 0x0001, /* mpllb cfg10 */
1736 .tx = { 0xbe88, /* tx cfg0 */
1737 0x9800, /* tx cfg1 */
1738 0x0000, /* tx cfg2 */
1740 .cmn = { 0x0500, /* cmn cfg0*/
1741 0x0005, /* cmn cfg1 */
1742 0x0000, /* cmn cfg2 */
1743 0x0000, /* cmn cfg3 */
1745 .mpllb = { 0xa0e0, /* mpllb cfg0 */
1746 0x7d80, /* mpllb cfg1 */
1747 0x0906, /* mpllb cfg2 */
1748 0xbe40, /* mpllb cfg3 */
1749 0x0000, /* mpllb cfg4 */
1750 0x0000, /* mpllb cfg5 */
1751 0x2200, /* mpllb cfg6 */
1752 0x0001, /* mpllb cfg7 */
1753 0x8000, /* mpllb cfg8 */
1754 0x0000, /* mpllb cfg9 */
1755 0x0001, /* mpllb cfg10 */
1761 .tx = { 0xbe88, /* tx cfg0 */
1762 0x9800, /* tx cfg1 */
1763 0x0000, /* tx cfg2 */
1765 .cmn = { 0x0500, /* cmn cfg0*/
1766 0x0005, /* cmn cfg1 */
1767 0x0000, /* cmn cfg2 */
1768 0x0000, /* cmn cfg3 */
1770 .mpllb = { 0x609a, /* mpllb cfg0 */
1771 0x7d40, /* mpllb cfg1 */
1772 0xca06, /* mpllb cfg2 */
1773 0xbe40, /* mpllb cfg3 */
1774 0x0000, /* mpllb cfg4 */
1775 0x0000, /* mpllb cfg5 */
1776 0x2200, /* mpllb cfg6 */
1777 0x0001, /* mpllb cfg7 */
1778 0x5800, /* mpllb cfg8 */
1779 0x0000, /* mpllb cfg9 */
1780 0x0001, /* mpllb cfg10 */
1786 .tx = { 0xbe88, /* tx cfg0 */
1787 0x9800, /* tx cfg1 */
1788 0x0000, /* tx cfg2 */
1790 .cmn = { 0x0500, /* cmn cfg0*/
1791 0x0005, /* cmn cfg1 */
1792 0x0000, /* cmn cfg2 */
1793 0x0000, /* cmn cfg3 */
1795 .mpllb = { 0x409a, /* mpllb cfg0 */
1796 0x7d20, /* mpllb cfg1 */
1797 0xca06, /* mpllb cfg2 */
1798 0xbe40, /* mpllb cfg3 */
1799 0x0000, /* mpllb cfg4 */
1800 0x0000, /* mpllb cfg5 */
1801 0x2200, /* mpllb cfg6 */
1802 0x0001, /* mpllb cfg7 */
1803 0x5800, /* mpllb cfg8 */
1804 0x0000, /* mpllb cfg9 */
1805 0x0001, /* mpllb cfg10 */
1811 .tx = { 0xbe88, /* tx cfg0 */
1812 0x9800, /* tx cfg1 */
1813 0x0000, /* tx cfg2 */
1815 .cmn = { 0x0500, /* cmn cfg0*/
1816 0x0005, /* cmn cfg1 */
1817 0x0000, /* cmn cfg2 */
1818 0x0000, /* cmn cfg3 */
1820 .mpllb = { 0x009a, /* mpllb cfg0 */
1821 0x7d08, /* mpllb cfg1 */
1822 0xca06, /* mpllb cfg2 */
1823 0xbe40, /* mpllb cfg3 */
1824 0x0000, /* mpllb cfg4 */
1825 0x0000, /* mpllb cfg5 */
1826 0x2200, /* mpllb cfg6 */
1827 0x0001, /* mpllb cfg7 */
1828 0x5800, /* mpllb cfg8 */
1829 0x0000, /* mpllb cfg9 */
1830 0x0001, /* mpllb cfg10 */
1836 .tx = { 0xbe98, /* tx cfg0 */
1837 0x8800, /* tx cfg1 */
1838 0x0000, /* tx cfg2 */
1840 .cmn = { 0x0500, /* cmn cfg0*/
1841 0x0005, /* cmn cfg1 */
1842 0x0000, /* cmn cfg2 */
1843 0x0000, /* cmn cfg3 */
1845 .mpllb = { 0x309c, /* mpllb cfg0 */
1846 0x2110, /* mpllb cfg1 */
1847 0xca06, /* mpllb cfg2 */
1848 0xbe40, /* mpllb cfg3 */
1849 0x0000, /* mpllb cfg4 */
1850 0x0000, /* mpllb cfg5 */
1851 0x2200, /* mpllb cfg6 */
1852 0x0001, /* mpllb cfg7 */
1853 0x2000, /* mpllb cfg8 */
1854 0x0000, /* mpllb cfg9 */
1855 0x0004, /* mpllb cfg10 */
1861 .tx = { 0xbe98, /* tx cfg0 */
1862 0x8800, /* tx cfg1 */
1863 0x0000, /* tx cfg2 */
1865 .cmn = { 0x0500, /* cmn cfg0*/
1866 0x0005, /* cmn cfg1 */
1867 0x0000, /* cmn cfg2 */
1868 0x0000, /* cmn cfg3 */
1870 .mpllb = { 0x109c, /* mpllb cfg0 */
1871 0x2108, /* mpllb cfg1 */
1872 0xca06, /* mpllb cfg2 */
1873 0xbe40, /* mpllb cfg3 */
1874 0x0000, /* mpllb cfg4 */
1875 0x0000, /* mpllb cfg5 */
1876 0x2200, /* mpllb cfg6 */
1877 0x0001, /* mpllb cfg7 */
1878 0x2000, /* mpllb cfg8 */
1879 0x0000, /* mpllb cfg9 */
1880 0x0004, /* mpllb cfg10 */
1886 .tx = { 0xbe98, /* tx cfg0 */
1887 0x8800, /* tx cfg1 */
1888 0x0000, /* tx cfg2 */
1890 .cmn = { 0x0500, /* cmn cfg0*/
1891 0x0005, /* cmn cfg1 */
1892 0x0000, /* cmn cfg2 */
1893 0x0000, /* cmn cfg3 */
1895 .mpllb = { 0x10d0, /* mpllb cfg0 */
1896 0x2108, /* mpllb cfg1 */
1897 0x4a06, /* mpllb cfg2 */
1898 0xbe40, /* mpllb cfg3 */
1899 0x0000, /* mpllb cfg4 */
1900 0x0000, /* mpllb cfg5 */
1901 0x2200, /* mpllb cfg6 */
1902 0x0003, /* mpllb cfg7 */
1903 0x2aaa, /* mpllb cfg8 */
1904 0x0002, /* mpllb cfg9 */
1905 0x0004, /* mpllb cfg10 */
1911 .tx = { 0xbe98, /* tx cfg0 */
1912 0x8800, /* tx cfg1 */
1913 0x0000, /* tx cfg2 */
1915 .cmn = { 0x0500, /* cmn cfg0*/
1916 0x0005, /* cmn cfg1 */
1917 0x0000, /* cmn cfg2 */
1918 0x0000, /* cmn cfg3 */
1920 .mpllb = { 0x1104, /* mpllb cfg0 */
1921 0x2108, /* mpllb cfg1 */
1922 0x0a06, /* mpllb cfg2 */
1923 0xbe40, /* mpllb cfg3 */
1924 0x0000, /* mpllb cfg4 */
1925 0x0000, /* mpllb cfg5 */
1926 0x2200, /* mpllb cfg6 */
1927 0x0003, /* mpllb cfg7 */
1928 0x3555, /* mpllb cfg8 */
1929 0x0001, /* mpllb cfg9 */
1930 0x0004, /* mpllb cfg10 */
1936 .tx = { 0xbe98, /* tx cfg0 */
1937 0x8800, /* tx cfg1 */
1938 0x0000, /* tx cfg2 */
1940 .cmn = { 0x0500, /* cmn cfg0*/
1941 0x0005, /* cmn cfg1 */
1942 0x0000, /* cmn cfg2 */
1943 0x0000, /* cmn cfg3 */
1945 .mpllb = { 0x1138, /* mpllb cfg0 */
1946 0x2108, /* mpllb cfg1 */
1947 0x5486, /* mpllb cfg2 */
1948 0xfe40, /* mpllb cfg3 */
1949 0x0000, /* mpllb cfg4 */
1950 0x0000, /* mpllb cfg5 */
1951 0x2200, /* mpllb cfg6 */
1952 0x0001, /* mpllb cfg7 */
1953 0x4000, /* mpllb cfg8 */
1954 0x0000, /* mpllb cfg9 */
1955 0x0004, /* mpllb cfg10 */
1978 for (i = 0; tables[i]; i++) { in intel_c10_phy_check_hdmi_link_rate()
1979 if (clock == tables[i]->clock) in intel_c10_phy_check_hdmi_link_rate()
1999 MISSING_CASE(encoder->type); in intel_c10pll_tables_get()
2006 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_c10pll_update_pll()
2007 struct intel_cx0pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll; in intel_c10pll_update_pll()
2014 pll_state->ssc_enabled = in intel_c10pll_update_pll()
2015 (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5); in intel_c10pll_update_pll()
2019 if (pll_state->ssc_enabled) in intel_c10pll_update_pll()
2022 drm_WARN_ON(&i915->drm, ARRAY_SIZE(pll_state->c10.pll) < 9); in intel_c10pll_update_pll()
2024 pll_state->c10.pll[i] = 0; in intel_c10pll_update_pll()
2035 return -EINVAL; in intel_c10pll_calc_state()
2037 for (i = 0; tables[i]; i++) { in intel_c10pll_calc_state()
2038 if (crtc_state->port_clock == tables[i]->clock) { in intel_c10pll_calc_state()
2039 crtc_state->dpll_hw_state.cx0pll.c10 = *tables[i]; in intel_c10pll_calc_state()
2041 crtc_state->dpll_hw_state.cx0pll.use_c10 = true; in intel_c10pll_calc_state()
2043 return 0; in intel_c10pll_calc_state()
2047 return -EINVAL; in intel_c10pll_calc_state()
2064 0, C10_VDR_CTRL_MSGBUS_ACCESS, in intel_c10pll_readout_hw_state()
2067 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10pll_readout_hw_state()
2068 pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i)); in intel_c10pll_readout_hw_state()
2070 pll_state->cmn = intel_cx0_read(encoder, lane, PHY_C10_VDR_CMN(0)); in intel_c10pll_readout_hw_state()
2071 pll_state->tx = intel_cx0_read(encoder, lane, PHY_C10_VDR_TX(0)); in intel_c10pll_readout_hw_state()
2080 const struct intel_c10pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c10; in intel_c10_pll_program()
2084 0, C10_VDR_CTRL_MSGBUS_ACCESS, in intel_c10_pll_program()
2087 /* Custom width needs to be programmed to 0 for both the phy lanes */ in intel_c10_pll_program()
2092 0, C10_VDR_CTRL_UPDATE_CFG, in intel_c10_pll_program()
2095 /* Program the pll values only for the master lane */ in intel_c10_pll_program()
2096 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10_pll_program()
2098 pll_state->pll[i], in intel_c10_pll_program()
2101 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED); in intel_c10_pll_program()
2102 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED); in intel_c10_pll_program()
2105 0, C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, in intel_c10_pll_program()
2114 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; in intel_c10pll_dump_hw_state()
2117 fracen = hw_state->pll[0] & C10_PLL0_FRACEN; in intel_c10pll_dump_hw_state()
2118 drm_dbg_kms(&i915->drm, "c10pll_hw_state: fracen: %s, ", in intel_c10pll_dump_hw_state()
2122 frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11]; in intel_c10pll_dump_hw_state()
2123 frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13]; in intel_c10pll_dump_hw_state()
2124 frac_den = hw_state->pll[10] << 8 | hw_state->pll[9]; in intel_c10pll_dump_hw_state()
2125 drm_dbg_kms(&i915->drm, "quot: %u, rem: %u, den: %u,\n", in intel_c10pll_dump_hw_state()
2129 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 | in intel_c10pll_dump_hw_state()
2130 hw_state->pll[2]) / 2 + 16; in intel_c10pll_dump_hw_state()
2131 tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]); in intel_c10pll_dump_hw_state()
2132 drm_dbg_kms(&i915->drm, in intel_c10pll_dump_hw_state()
2135 drm_dbg_kms(&i915->drm, "c10pll_rawhw_state:"); in intel_c10pll_dump_hw_state()
2136 drm_dbg_kms(&i915->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, hw_state->cmn); in intel_c10pll_dump_hw_state()
2138 BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4); in intel_c10pll_dump_hw_state()
2139 for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4) in intel_c10pll_dump_hw_state()
2140 drm_dbg_kms(&i915->drm, "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n", in intel_c10pll_dump_hw_state()
2141 i, hw_state->pll[i], i + 1, hw_state->pll[i + 1], in intel_c10pll_dump_hw_state()
2142 i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]); in intel_c10pll_dump_hw_state()
2159 return -EINVAL; in intel_c20_compute_hdmi_tmds_pll()
2168 mpll_fracn_quot = (multiplier >> 16) & 0xFFFF; in intel_c20_compute_hdmi_tmds_pll()
2169 mpll_fracn_rem = multiplier & 0xFFFF; in intel_c20_compute_hdmi_tmds_pll()
2183 pll_state->clock = pixel_clock; in intel_c20_compute_hdmi_tmds_pll()
2184 pll_state->tx[0] = 0xbe88; in intel_c20_compute_hdmi_tmds_pll()
2185 pll_state->tx[1] = 0x9800; in intel_c20_compute_hdmi_tmds_pll()
2186 pll_state->tx[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2187 pll_state->cmn[0] = 0x0500; in intel_c20_compute_hdmi_tmds_pll()
2188 pll_state->cmn[1] = 0x0005; in intel_c20_compute_hdmi_tmds_pll()
2189 pll_state->cmn[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2190 pll_state->cmn[3] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2191 pll_state->mpllb[0] = (MPLL_TX_CLK_DIV(mpll_tx_clk_div) | in intel_c20_compute_hdmi_tmds_pll()
2193 pll_state->mpllb[1] = (CAL_DAC_CODE(CAL_DAC_CODE_31) | in intel_c20_compute_hdmi_tmds_pll()
2196 pll_state->mpllb[2] = (MPLLB_ANA_FREQ_VCO(mpllb_ana_freq_vco) | in intel_c20_compute_hdmi_tmds_pll()
2199 pll_state->mpllb[3] = (V2I(V2I_2) | in intel_c20_compute_hdmi_tmds_pll()
2202 pll_state->mpllb[4] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2203 pll_state->mpllb[5] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2204 pll_state->mpllb[6] = (C20_MPLLB_FRACEN | SSC_UP_SPREAD); in intel_c20_compute_hdmi_tmds_pll()
2205 pll_state->mpllb[7] = MPLL_FRACN_DEN; in intel_c20_compute_hdmi_tmds_pll()
2206 pll_state->mpllb[8] = mpll_fracn_quot; in intel_c20_compute_hdmi_tmds_pll()
2207 pll_state->mpllb[9] = mpll_fracn_rem; in intel_c20_compute_hdmi_tmds_pll()
2208 pll_state->mpllb[10] = HDMI_DIV(HDMI_DIV_1); in intel_c20_compute_hdmi_tmds_pll()
2210 return 0; in intel_c20_compute_hdmi_tmds_pll()
2218 for (i = 0; tables[i]; i++) { in intel_c20_phy_check_hdmi_link_rate()
2219 if (clock == tables[i]->clock) in intel_c20_phy_check_hdmi_link_rate()
2233 if (intel_encoder_is_c10phy(&dig_port->base)) in intel_cx0_phy_check_hdmi_link_rate()
2242 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_c20_pll_tables_get()
2257 MISSING_CASE(encoder->type); in intel_c20_pll_tables_get()
2269 if (intel_c20_compute_hdmi_tmds_pll(crtc_state->port_clock, in intel_c20pll_calc_state()
2270 &crtc_state->dpll_hw_state.cx0pll.c20) == 0) in intel_c20pll_calc_state()
2271 return 0; in intel_c20pll_calc_state()
2276 return -EINVAL; in intel_c20pll_calc_state()
2278 for (i = 0; tables[i]; i++) { in intel_c20pll_calc_state()
2279 if (crtc_state->port_clock == tables[i]->clock) { in intel_c20pll_calc_state()
2280 crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i]; in intel_c20pll_calc_state()
2281 crtc_state->dpll_hw_state.cx0pll.use_c10 = false; in intel_c20pll_calc_state()
2282 return 0; in intel_c20pll_calc_state()
2286 return -EINVAL; in intel_c20pll_calc_state()
2299 return state->tx[0] & C20_PHY_USE_MPLLB; in intel_c20phy_use_mpllb()
2312 unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]); in intel_c20pll_calc_port_clock()
2316 frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2317 frac_quot = pll_state->mpllb[8]; in intel_c20pll_calc_port_clock()
2318 frac_rem = pll_state->mpllb[9]; in intel_c20pll_calc_port_clock()
2319 frac_den = pll_state->mpllb[7]; in intel_c20pll_calc_port_clock()
2320 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2321 tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2322 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2323 fb_clk_div4_en = 0; in intel_c20pll_calc_port_clock()
2326 frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]); in intel_c20pll_calc_port_clock()
2327 frac_quot = pll_state->mplla[8]; in intel_c20pll_calc_port_clock()
2328 frac_rem = pll_state->mplla[9]; in intel_c20pll_calc_port_clock()
2329 frac_den = pll_state->mplla[7]; in intel_c20pll_calc_port_clock()
2330 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2331 tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]); in intel_c20pll_calc_port_clock()
2332 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]); in intel_c20pll_calc_port_clock()
2333 fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2339 frac = 0; in intel_c20pll_calc_port_clock()
2342 vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10); in intel_c20pll_calc_port_clock()
2353 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_c20pll_readout_hw_state()
2361 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { in intel_c20pll_readout_hw_state()
2363 pll_state->tx[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2367 pll_state->tx[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2373 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { in intel_c20pll_readout_hw_state()
2375 pll_state->cmn[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2379 pll_state->cmn[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2386 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { in intel_c20pll_readout_hw_state()
2388 pll_state->mpllb[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2392 pll_state->mpllb[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2398 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { in intel_c20pll_readout_hw_state()
2400 pll_state->mplla[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2404 pll_state->mplla[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2410 pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state); in intel_c20pll_readout_hw_state()
2420 drm_dbg_kms(&i915->drm, "c20pll_hw_state:\n"); in intel_c20pll_dump_hw_state()
2421 drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2422 hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); in intel_c20pll_dump_hw_state()
2423 drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2424 hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); in intel_c20pll_dump_hw_state()
2427 for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) in intel_c20pll_dump_hw_state()
2428 drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]); in intel_c20pll_dump_hw_state()
2430 for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) in intel_c20pll_dump_hw_state()
2431 drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]); in intel_c20pll_dump_hw_state()
2438 if (hw_state->use_c10) in intel_cx0pll_dump_hw_state()
2439 intel_c10pll_dump_hw_state(i915, &hw_state->c10); in intel_cx0pll_dump_hw_state()
2441 intel_c20pll_dump_hw_state(i915, &hw_state->c20); in intel_cx0pll_dump_hw_state()
2448 return 0; in intel_c20_get_dp_rate()
2463 case 1000000: /* 10 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2465 case 1350000: /* 13.5 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2467 case 2000000: /* 20 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2475 return 0; in intel_c20_get_dp_rate()
2482 return 0; in intel_c20_get_hdmi_rate()
2495 return 0; in intel_c20_get_hdmi_rate()
2501 /* DP2.0 clock rates */ in is_dp2()
2527 /* TODO: optimize re-calibration in legacy mode */ in intel_c20_protocol_switch_valid()
2538 return 0; in intel_get_c20_custom_width()
2545 const struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; in intel_c20_pll_program()
2548 u32 clock = crtc_state->port_clock; in intel_c20_pll_program()
2556 cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(0); in intel_c20_pll_program()
2560 * the lane #0 MPLLB CAL_DONE_BANK DP2.0 10G and 20G rates enable MPLLA. in intel_c20_pll_program()
2564 for (i = 0; i < 4; i++) in intel_c20_pll_program()
2565 intel_c20_sram_write(encoder, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0); in intel_c20_pll_program()
2571 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { in intel_c20_pll_program()
2575 pll_state->tx[i]); in intel_c20_pll_program()
2579 pll_state->tx[i]); in intel_c20_pll_program()
2583 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { in intel_c20_pll_program()
2587 pll_state->cmn[i]); in intel_c20_pll_program()
2591 pll_state->cmn[i]); in intel_c20_pll_program()
2596 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { in intel_c20_pll_program()
2600 pll_state->mpllb[i]); in intel_c20_pll_program()
2604 pll_state->mpllb[i]); in intel_c20_pll_program()
2607 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { in intel_c20_pll_program()
2611 pll_state->mplla[i]); in intel_c20_pll_program()
2615 pll_state->mplla[i]); in intel_c20_pll_program()
2634 is_hdmi_frl(clock) ? BIT(7) : 0, in intel_c20_pll_program()
2647 BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED); in intel_c20_pll_program()
2653 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; in intel_c10pll_calc_port_clock()
2655 int tmpclk = 0; in intel_c10pll_calc_port_clock()
2657 if (pll_state->pll[0] & C10_PLL0_FRACEN) { in intel_c10pll_calc_port_clock()
2658 frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11]; in intel_c10pll_calc_port_clock()
2659 frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13]; in intel_c10pll_calc_port_clock()
2660 frac_den = pll_state->pll[10] << 8 | pll_state->pll[9]; in intel_c10pll_calc_port_clock()
2663 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 | in intel_c10pll_calc_port_clock()
2664 pll_state->pll[2]) / 2 + 16; in intel_c10pll_calc_port_clock()
2666 tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]); in intel_c10pll_calc_port_clock()
2667 hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]); in intel_c10pll_calc_port_clock()
2681 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_program_port_clock_ctl()
2682 u32 val = 0; in intel_program_port_clock_ctl()
2684 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), in intel_program_port_clock_ctl()
2686 lane_reversal ? XELPDP_PORT_REVERSAL : 0); in intel_program_port_clock_ctl()
2694 is_hdmi_frl(crtc_state->port_clock)) in intel_program_port_clock_ctl()
2700 /* DP2.0 10G and 20G rates enable MPLLA*/ in intel_program_port_clock_ctl()
2701 if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000) in intel_program_port_clock_ctl()
2702 val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0; in intel_program_port_clock_ctl()
2704 val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; in intel_program_port_clock_ctl()
2706 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_program_port_clock_ctl()
2714 u32 val = 0; in intel_cx0_get_powerdown_update()
2715 int lane = 0; in intel_cx0_get_powerdown_update()
2725 u32 val = 0; in intel_cx0_get_powerdown_state()
2726 int lane = 0; in intel_cx0_get_powerdown_state()
2737 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_powerdown_change_sequence()
2738 enum port port = encoder->port; in intel_cx0_powerdown_change_sequence()
2752 drm_dbg_kms(&i915->drm, in intel_cx0_powerdown_change_sequence()
2764 intel_cx0_get_powerdown_update(lane_mask), 0, in intel_cx0_powerdown_change_sequence()
2765 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL)) in intel_cx0_powerdown_change_sequence()
2766 drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n", in intel_cx0_powerdown_change_sequence()
2772 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_setup_powerdown()
2773 enum port port = encoder->port; in intel_cx0_setup_powerdown()
2782 XELPDP_PLL_LANE_STAGGERING_DELAY(0)); in intel_cx0_setup_powerdown()
2787 u32 val = 0; in intel_cx0_get_pclk_refclk_request()
2788 int lane = 0; in intel_cx0_get_pclk_refclk_request()
2798 u32 val = 0; in intel_cx0_get_pclk_refclk_ack()
2799 int lane = 0; in intel_cx0_get_pclk_refclk_ack()
2810 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_lane_reset()
2811 enum port port = encoder->port; in intel_cx0_phy_lane_reset()
2816 ? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1) in intel_cx0_phy_lane_reset()
2817 : XELPDP_LANE_PIPE_RESET(0); in intel_cx0_phy_lane_reset()
2819 ? (XELPDP_LANE_PHY_CURRENT_STATUS(0) | in intel_cx0_phy_lane_reset()
2821 : XELPDP_LANE_PHY_CURRENT_STATUS(0); in intel_cx0_phy_lane_reset()
2826 XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL)) in intel_cx0_phy_lane_reset()
2827 drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n", in intel_cx0_phy_lane_reset()
2835 XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL)) in intel_cx0_phy_lane_reset()
2836 drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n", in intel_cx0_phy_lane_reset()
2846 XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL)) in intel_cx0_phy_lane_reset()
2847 drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n", in intel_cx0_phy_lane_reset()
2854 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset, 0); in intel_cx0_phy_lane_reset()
2859 drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n", in intel_cx0_phy_lane_reset()
2874 PHY_C10_VDR_CONTROL(1), 0, in intel_cx0_program_phy_lane()
2879 disables = REG_GENMASK8(3, 0) >> lane_count; in intel_cx0_program_phy_lane()
2881 disables = REG_GENMASK8(3, 0) << lane_count; in intel_cx0_program_phy_lane()
2884 disables &= ~REG_GENMASK8(1, 0); in intel_cx0_program_phy_lane()
2885 disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1); in intel_cx0_program_phy_lane()
2888 for (i = 0; i < 4; i++) { in intel_cx0_program_phy_lane()
2897 disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0, in intel_cx0_program_phy_lane()
2903 PHY_C10_VDR_CONTROL(1), 0, in intel_cx0_program_phy_lane()
2910 u32 val = 0; in intel_cx0_get_pclk_pll_request()
2911 int lane = 0; in intel_cx0_get_pclk_pll_request()
2921 u32 val = 0; in intel_cx0_get_pclk_pll_ack()
2922 int lane = 0; in intel_cx0_get_pclk_pll_ack()
2933 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0pll_enable()
2936 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; in intel_cx0pll_enable()
2958 * 4. Program PORT_MSGBUS_TIMER register's Message Bus Timer field to 0xA000. in intel_cx0pll_enable()
2963 /* 5. Program PHY internal PLL internal registers. */ in intel_cx0pll_enable()
2973 intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal); in intel_cx0pll_enable()
2976 * 7. Follow the Display Voltage Frequency Switching - Sequence in intel_cx0pll_enable()
2984 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), in intel_cx0pll_enable()
2985 crtc_state->port_clock); in intel_cx0pll_enable()
2988 * 9. Set PORT_CLOCK_CTL register PCLK PLL Request in intel_cx0pll_enable()
2989 * LN<Lane for maxPCLK> to "1" to enable PLL. in intel_cx0pll_enable()
2991 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_cx0pll_enable()
2995 /* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */ in intel_cx0pll_enable()
2996 if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_cx0pll_enable()
2999 XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL)) in intel_cx0pll_enable()
3000 drm_warn(&i915->drm, "Port %c PLL not locked after %dus.\n", in intel_cx0pll_enable()
3008 /* TODO: enable TBT-ALT mode */ in intel_cx0pll_enable()
3014 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_mtl_tbt_calc_port_clock()
3016 u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port)); in intel_mtl_tbt_calc_port_clock()
3020 drm_WARN_ON(&i915->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE)); in intel_mtl_tbt_calc_port_clock()
3021 drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_REQUEST)); in intel_mtl_tbt_calc_port_clock()
3022 drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_ACK)); in intel_mtl_tbt_calc_port_clock()
3059 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_mtl_tbt_pll_enable()
3061 u32 val = 0; in intel_mtl_tbt_pll_enable()
3067 val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock)); in intel_mtl_tbt_pll_enable()
3069 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_mtl_tbt_pll_enable()
3073 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port)); in intel_mtl_tbt_pll_enable()
3076 * 3. Follow the Display Voltage Frequency Switching - Sequence in intel_mtl_tbt_pll_enable()
3081 * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL. in intel_mtl_tbt_pll_enable()
3084 intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), val); in intel_mtl_tbt_pll_enable()
3087 if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_mtl_tbt_pll_enable()
3090 100, 0, NULL)) in intel_mtl_tbt_pll_enable()
3091 drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n", in intel_mtl_tbt_pll_enable()
3092 encoder->base.base.id, encoder->base.name, phy_name(phy)); in intel_mtl_tbt_pll_enable()
3103 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), in intel_mtl_tbt_pll_enable()
3104 crtc_state->port_clock); in intel_mtl_tbt_pll_enable()
3120 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in cx0_power_control_disable_val()
3125 if (IS_BATTLEMAGE(i915) && encoder->port == PORT_A) in cx0_power_control_disable_val()
3133 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0pll_disable()
3147 * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK> in intel_cx0pll_disable()
3148 * to "0" to disable PLL. in intel_cx0pll_disable()
3150 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_cx0pll_disable()
3152 intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0); in intel_cx0pll_disable()
3154 /* 4. Program DDI_CLK_VALFREQ to 0. */ in intel_cx0pll_disable()
3155 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0); in intel_cx0pll_disable()
3158 * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0". in intel_cx0pll_disable()
3160 if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_cx0pll_disable()
3162 intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0, in intel_cx0pll_disable()
3163 XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL)) in intel_cx0pll_disable()
3164 drm_warn(&i915->drm, "Port %c PLL not unlocked after %dus.\n", in intel_cx0pll_disable()
3173 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_cx0pll_disable()
3174 XELPDP_DDI_CLOCK_SELECT_MASK, 0); in intel_cx0pll_disable()
3175 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_cx0pll_disable()
3176 XELPDP_FORWARD_CLOCK_UNGATE, 0); in intel_cx0pll_disable()
3183 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_mtl_tbt_pll_disable()
3192 * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL. in intel_mtl_tbt_pll_disable()
3194 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_mtl_tbt_pll_disable()
3195 XELPDP_TBT_CLOCK_REQUEST, 0); in intel_mtl_tbt_pll_disable()
3197 /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */ in intel_mtl_tbt_pll_disable()
3198 if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_mtl_tbt_pll_disable()
3199 XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL)) in intel_mtl_tbt_pll_disable()
3200 drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n", in intel_mtl_tbt_pll_disable()
3201 encoder->base.base.id, encoder->base.name, phy_name(phy)); in intel_mtl_tbt_pll_disable()
3211 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_mtl_tbt_pll_disable()
3213 XELPDP_FORWARD_CLOCK_UNGATE, 0); in intel_mtl_tbt_pll_disable()
3215 /* 6. Program DDI_CLK_VALFREQ to 0. */ in intel_mtl_tbt_pll_disable()
3216 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0); in intel_mtl_tbt_pll_disable()
3233 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_mtl_port_pll_type()
3235 * TODO: Determine the PLL type from the SW state, once MTL PLL in intel_mtl_port_pll_type()
3238 u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port)); in intel_mtl_port_pll_type()
3253 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_c10pll_state_verify()
3254 const struct intel_c10pll_state *mpllb_sw_state = &state->dpll_hw_state.cx0pll.c10; in intel_c10pll_state_verify()
3257 for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { in intel_c10pll_state_verify()
3258 u8 expected = mpllb_sw_state->pll[i]; in intel_c10pll_state_verify()
3260 I915_STATE_WARN(i915, mpllb_hw_state->pll[i] != expected, in intel_c10pll_state_verify()
3261 "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)", in intel_c10pll_state_verify()
3262 crtc->base.base.id, crtc->base.name, i, in intel_c10pll_state_verify()
3263 expected, mpllb_hw_state->pll[i]); in intel_c10pll_state_verify()
3266 I915_STATE_WARN(i915, mpllb_hw_state->tx != mpllb_sw_state->tx, in intel_c10pll_state_verify()
3267 "[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)", in intel_c10pll_state_verify()
3268 crtc->base.base.id, crtc->base.name, in intel_c10pll_state_verify()
3269 mpllb_sw_state->tx, mpllb_hw_state->tx); in intel_c10pll_state_verify()
3271 I915_STATE_WARN(i915, mpllb_hw_state->cmn != mpllb_sw_state->cmn, in intel_c10pll_state_verify()
3272 "[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)", in intel_c10pll_state_verify()
3273 crtc->base.base.id, crtc->base.name, in intel_c10pll_state_verify()
3274 mpllb_sw_state->cmn, mpllb_hw_state->cmn); in intel_c10pll_state_verify()
3280 pll_state->use_c10 = false; in intel_cx0pll_readout_hw_state()
3282 pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)); in intel_cx0pll_readout_hw_state()
3283 if (pll_state->tbt_mode) in intel_cx0pll_readout_hw_state()
3287 intel_c10pll_readout_hw_state(encoder, &pll_state->c10); in intel_cx0pll_readout_hw_state()
3288 pll_state->use_c10 = true; in intel_cx0pll_readout_hw_state()
3290 intel_c20pll_readout_hw_state(encoder, &pll_state->c20); in intel_cx0pll_readout_hw_state()
3297 if (a->tx != b->tx) in mtl_compare_hw_state_c10()
3300 if (a->cmn != b->cmn) in mtl_compare_hw_state_c10()
3303 if (memcmp(&a->pll, &b->pll, sizeof(a->pll)) != 0) in mtl_compare_hw_state_c10()
3312 if (memcmp(&a->tx, &b->tx, sizeof(a->tx)) != 0) in mtl_compare_hw_state_c20()
3315 if (memcmp(&a->cmn, &b->cmn, sizeof(a->cmn)) != 0) in mtl_compare_hw_state_c20()
3318 if (a->tx[0] & C20_PHY_USE_MPLLB) { in mtl_compare_hw_state_c20()
3319 if (memcmp(&a->mpllb, &b->mpllb, sizeof(a->mpllb)) != 0) in mtl_compare_hw_state_c20()
3322 if (memcmp(&a->mplla, &b->mplla, sizeof(a->mplla)) != 0) in mtl_compare_hw_state_c20()
3332 if (a->tbt_mode || b->tbt_mode) in intel_cx0pll_compare_hw_state()
3335 if (a->use_c10 != b->use_c10) in intel_cx0pll_compare_hw_state()
3338 if (a->use_c10) in intel_cx0pll_compare_hw_state()
3339 return mtl_compare_hw_state_c10(&a->c10, in intel_cx0pll_compare_hw_state()
3340 &b->c10); in intel_cx0pll_compare_hw_state()
3342 return mtl_compare_hw_state_c20(&a->c20, in intel_cx0pll_compare_hw_state()
3343 &b->c20); in intel_cx0pll_compare_hw_state()
3350 return intel_c10pll_calc_port_clock(encoder, &pll_state->c10); in intel_cx0pll_calc_port_clock()
3352 return intel_c20pll_calc_port_clock(encoder, &pll_state->c20); in intel_cx0pll_calc_port_clock()
3360 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_c20pll_state_verify()
3361 const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20; in intel_c20pll_state_verify()
3367 I915_STATE_WARN(i915, mpll_hw_state->clock != clock, in intel_c20pll_state_verify()
3369 crtc->base.base.id, crtc->base.name, in intel_c20pll_state_verify()
3370 mpll_sw_state->clock, mpll_hw_state->clock); in intel_c20pll_state_verify()
3374 crtc->base.base.id, crtc->base.name, in intel_c20pll_state_verify()
3378 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) { in intel_c20pll_state_verify()
3379 I915_STATE_WARN(i915, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i], in intel_c20pll_state_verify()
3380 "[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)", in intel_c20pll_state_verify()
3381 crtc->base.base.id, crtc->base.name, i, in intel_c20pll_state_verify()
3382 mpll_sw_state->mpllb[i], mpll_hw_state->mpllb[i]); in intel_c20pll_state_verify()
3385 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) { in intel_c20pll_state_verify()
3386 I915_STATE_WARN(i915, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i], in intel_c20pll_state_verify()
3387 "[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)", in intel_c20pll_state_verify()
3388 crtc->base.base.id, crtc->base.name, i, in intel_c20pll_state_verify()
3389 mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]); in intel_c20pll_state_verify()
3393 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) { in intel_c20pll_state_verify()
3394 I915_STATE_WARN(i915, mpll_hw_state->tx[i] != mpll_sw_state->tx[i], in intel_c20pll_state_verify()
3395 "[CRTC:%d:%s] mismatch in C20: Register TX[%i] (expected 0x%04x, found 0x%04x)", in intel_c20pll_state_verify()
3396 crtc->base.base.id, crtc->base.name, i, in intel_c20pll_state_verify()
3397 mpll_sw_state->tx[i], mpll_hw_state->tx[i]); in intel_c20pll_state_verify()
3400 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) { in intel_c20pll_state_verify()
3401 I915_STATE_WARN(i915, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i], in intel_c20pll_state_verify()
3402 "[CRTC:%d:%s] mismatch in C20: Register CMN[%i] (expected 0x%04x, found 0x%04x)", in intel_c20pll_state_verify()
3403 crtc->base.base.id, crtc->base.name, i, in intel_c20pll_state_verify()
3404 mpll_sw_state->cmn[i], mpll_hw_state->cmn[i]); in intel_c20pll_state_verify()
3411 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_cx0pll_state_verify()
3420 if (!new_crtc_state->hw.active) in intel_cx0pll_state_verify()