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/linux-6.12.1/drivers/soc/mediatek/
Dmtk-mmsys.c14 #include <linux/soc/mediatek/mtk-mmsys.h>
16 #include "mtk-mmsys.h"
17 #include "mt8167-mmsys.h"
18 #include "mt8173-mmsys.h"
19 #include "mt8183-mmsys.h"
20 #include "mt8186-mmsys.h"
21 #include "mt8188-mmsys.h"
22 #include "mt8192-mmsys.h"
23 #include "mt8195-mmsys.h"
24 #include "mt8365-mmsys.h"
[all …]
Dmtk-mmsys.h92 * struct mtk_mmsys_driver_data - Settings of the mmsys
93 * @clk_driver: Clock driver name that the mmsys is using
95 * @routes: Routing table of the mmsys.
100 * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe)
115 * Each MMSYS (multi-media system) may have different settings, they may use
DKconfig53 tristate "MediaTek MMSYS Support"
59 Subsystem (MMSYS).
/linux-6.12.1/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,mmsys.yaml4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#
7 title: MediaTek mmsys controller
13 The MediaTek mmsys system controller provides clock control, routing control,
14 and miscellaneous control in mmsys partition.
24 - mediatek,mt2701-mmsys
25 - mediatek,mt2712-mmsys
26 - mediatek,mt6765-mmsys
27 - mediatek,mt6779-mmsys
28 - mediatek,mt6795-mmsys
29 - mediatek,mt6797-mmsys
[all …]
/linux-6.12.1/arch/arm/boot/dts/mediatek/
Dmt7623n.dtsi51 mmsys: syscon@14000000 { label
52 compatible = "mediatek,mt7623-mmsys",
53 "mediatek,mt2701-mmsys",
65 clocks = <&mmsys CLK_MM_SMI_LARB0>,
66 <&mmsys CLK_MM_SMI_LARB0>;
133 <&mmsys CLK_MM_SMI_COMMON>,
144 clocks = <&mmsys CLK_MM_DISP_OVL>;
153 clocks = <&mmsys CLK_MM_DISP_RDMA>;
162 clocks = <&mmsys CLK_MM_DISP_WDMA>;
171 clocks = <&mmsys CLK_MM_MDP_BLS_26M>,
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/media/
Dmediatek-mdp.txt36 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
37 <&mmsys CLK_MM_MUTEX_32K>;
46 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
47 <&mmsys CLK_MM_MUTEX_32K>;
55 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
62 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
69 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
76 clocks = <&mmsys CLK_MM_MDP_WDMA>;
84 clocks = <&mmsys CLK_MM_MDP_WROT0>;
92 clocks = <&mmsys CLK_MM_MDP_WROT1>;
Dmediatek,mdp3-rdma.yaml18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
162 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
163 <&mmsys CLK_MM_MDP_RSZ1>;
/linux-6.12.1/drivers/clk/mediatek/
DKconfig30 bool "Clock driver for MediaTek MT2701 mmsys"
33 This driver supports MediaTek MT2701 mmsys clocks.
110 tristate "Clock driver for MediaTek MT2712 mmsys"
113 This driver supports MediaTek MT2712 mmsys clocks.
154 tristate "Clock driver for MediaTek MT6765 mmsys"
157 This driver supports MediaTek MT6765 mmsys clocks.
222 tristate "Clock driver for MediaTek MT6779 mmsys"
225 This driver supports MediaTek MT6779 mmsys clocks.
287 tristate "Clock driver for MediaTek MT6795 mmsys"
291 This driver supports MediaTek MT6795 mmsys clocks.
[all …]
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi996 mmsys: syscon@14000000 { label
997 compatible = "mediatek,mt8173-mmsys", "syscon";
1013 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
1014 <&mmsys CLK_MM_MUTEX_32K>;
1023 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
1024 <&mmsys CLK_MM_MUTEX_32K>;
1032 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
1039 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
1046 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
1053 clocks = <&mmsys CLK_MM_MDP_WDMA>;
[all …]
Dmt6795.dtsi719 mmsys: syscon@14000000 { label
720 compatible = "mediatek,mt6795-mmsys", "syscon";
737 clocks = <&mmsys CLK_MM_DISP_OVL0>;
747 clocks = <&mmsys CLK_MM_DISP_OVL1>;
757 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
767 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
777 clocks = <&mmsys CLK_MM_DISP_RDMA2>;
787 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
797 clocks = <&mmsys CLK_MM_DISP_WDMA1>;
807 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
[all …]
Dmt8167.dtsi127 mmsys: syscon@14000000 { label
128 compatible = "mediatek,mt8167-mmsys", "syscon";
136 clocks = <&mmsys CLK_MM_SMI_COMMON>,
137 <&mmsys CLK_MM_SMI_COMMON>;
146 clocks = <&mmsys CLK_MM_SMI_LARB0>,
147 <&mmsys CLK_MM_SMI_LARB0>;
Dmt8183.dtsi906 <&mmsys CLK_MM_SMI_COMMON>,
907 <&mmsys CLK_MM_SMI_LARB0>,
908 <&mmsys CLK_MM_SMI_LARB1>,
909 <&mmsys CLK_MM_GALS_COMM0>,
910 <&mmsys CLK_MM_GALS_COMM1>,
911 <&mmsys CLK_MM_GALS_CCU2MM>,
912 <&mmsys CLK_MM_GALS_IPU12MM>,
913 <&mmsys CLK_MM_GALS_IMG2MM>,
914 <&mmsys CLK_MM_GALS_CAM2MM>,
915 <&mmsys CLK_MM_GALS_IPU2MM>;
[all …]
Dmt8365.dtsi319 <&mmsys CLK_MM_MM_SMI_COMMON>,
320 <&mmsys CLK_MM_MM_SMI_COMM0>,
321 <&mmsys CLK_MM_MM_SMI_COMM1>,
322 <&mmsys CLK_MM_MM_SMI_LARB0>;
730 mmsys: syscon@14000000 { label
731 compatible = "mediatek,mt8365-mmsys", "syscon";
739 clocks = <&mmsys CLK_MM_MM_SMI_COMMON>,
740 <&mmsys CLK_MM_MM_SMI_COMMON>,
741 <&mmsys CLK_MM_MM_SMI_COMM0>,
742 <&mmsys CLK_MM_MM_SMI_COMM1>;
[all …]
Dmt8192.dtsi573 <&mmsys CLK_MM_SMI_INFRA>,
574 <&mmsys CLK_MM_SMI_COMMON>,
575 <&mmsys CLK_MM_SMI_GALS>,
576 <&mmsys CLK_MM_SMI_IOMMU>;
1452 mmsys: syscon@14000000 { label
1453 compatible = "mediatek,mt8192-mmsys", "syscon";
1466 clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
1476 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1477 <&mmsys CLK_MM_SMI_INFRA>,
1478 <&mmsys CLK_MM_SMI_GALS>,
[all …]
Dmt8186.dtsi984 <&mmsys CLK_MM_SMI_INFRA>,
985 <&mmsys CLK_MM_SMI_COMMON>,
986 <&mmsys CLK_MM_SMI_GALS>,
987 <&mmsys CLK_MM_SMI_IOMMU>;
1763 mmsys: syscon@14000000 { label
1764 compatible = "mediatek,mt8186-mmsys", "syscon";
1776 clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
1787 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>,
1788 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>;
1796 clocks = <&mmsys CLK_MM_SMI_COMMON>,
[all …]
Dmt2712e.dtsi994 mmsys: syscon@14000000 { label
995 compatible = "mediatek,mt2712-mmsys", "syscon";
1006 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1007 <&mmsys CLK_MM_SMI_LARB0>;
1015 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1016 <&mmsys CLK_MM_SMI_COMMON>;
1026 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1027 <&mmsys CLK_MM_SMI_LARB4>;
1037 clocks = <&mmsys CLK_MM_SMI_LARB5>,
1038 <&mmsys CLK_MM_SMI_LARB5>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,hdmi.yaml103 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
104 <&mmsys CLK_MM_HDMI_PLLCK>,
105 <&mmsys CLK_MM_HDMI_AUDIO>,
106 <&mmsys CLK_MM_HDMI_SPDIF>;
112 mediatek,syscon-hdmi = <&mmsys 0x900>;
Dmediatek,dsi.yaml111 clocks = <&mmsys CLK_MM_DSI0_MM>,
112 <&mmsys CLK_MM_DSI0_IF>,
115 resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
Dmediatek,od.yaml18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
59 clocks = <&mmsys CLK_MM_DISP_OD>;
Dmediatek,ufoe.yaml19 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
69 clocks = <&mmsys CLK_MM_DISP_UFOE>;
Dmediatek,postmask.yaml18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
80 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
/linux-6.12.1/drivers/gpu/drm/mediatek/
Dmtk_drm_drv.c330 { .compatible = "mediatek,mt2701-mmsys",
332 { .compatible = "mediatek,mt7623-mmsys",
334 { .compatible = "mediatek,mt2712-mmsys",
336 { .compatible = "mediatek,mt8167-mmsys",
338 { .compatible = "mediatek,mt8173-mmsys",
340 { .compatible = "mediatek,mt8183-mmsys",
342 { .compatible = "mediatek,mt8186-mmsys",
348 { .compatible = "mediatek,mt8192-mmsys",
350 { .compatible = "mediatek,mt8195-mmsys",
496 * 2. For multi mmsys architecture, crtc path data are located in in mtk_drm_kms_init()
[all …]
/linux-6.12.1/drivers/interconnect/mediatek/
Dmt8183.c40 static struct mtk_icc_node mmsys = { variable
41 .name = "mmsys",
108 [MASTER_MMSYS] = &mmsys,
Dmt8195.c40 static struct mtk_icc_node mmsys = { variable
41 .name = "mmsys",
215 .name = "hrt-mmsys",
282 [MASTER_MMSYS] = &mmsys,
/linux-6.12.1/Documentation/devicetree/bindings/pwm/
Dmediatek,pwm-disp.yaml77 clocks = <&mmsys CLK_MM_DISP_PWM026M>,
78 <&mmsys CLK_MM_DISP_PWM0MM>;

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