Lines Matching full:mmsys
984 <&mmsys CLK_MM_SMI_INFRA>,
985 <&mmsys CLK_MM_SMI_COMMON>,
986 <&mmsys CLK_MM_SMI_GALS>,
987 <&mmsys CLK_MM_SMI_IOMMU>;
1763 mmsys: syscon@14000000 { label
1764 compatible = "mediatek,mt8186-mmsys", "syscon";
1776 clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
1787 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>,
1788 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>;
1796 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1797 <&mmsys CLK_MM_SMI_COMMON>;
1807 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1808 <&mmsys CLK_MM_SMI_COMMON>;
1818 clocks = <&mmsys CLK_MM_DISP_OVL0>;
1828 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
1838 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1848 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1858 <&mmsys CLK_MM_DISP_DPI>,
1875 clocks = <&mmsys CLK_MM_DISP_CCORR0>;
1884 clocks = <&mmsys CLK_MM_DISP_AAL0>;
1893 clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
1903 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
1912 clocks = <&mmsys CLK_MM_DISP_DITHER0>;
1921 clocks = <&mmsys CLK_MM_DSI0>,
1922 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>,
1927 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>;
1940 clocks = <&mmsys CLK_MM_SMI_IOMMU>;
1954 clocks = <&mmsys CLK_MM_DISP_RDMA1>;