Lines Matching full:mmsys
719 mmsys: syscon@14000000 { label
720 compatible = "mediatek,mt6795-mmsys", "syscon";
737 clocks = <&mmsys CLK_MM_DISP_OVL0>;
747 clocks = <&mmsys CLK_MM_DISP_OVL1>;
757 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
767 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
777 clocks = <&mmsys CLK_MM_DISP_RDMA2>;
787 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
797 clocks = <&mmsys CLK_MM_DISP_WDMA1>;
807 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
816 clocks = <&mmsys CLK_MM_DISP_COLOR1>;
825 clocks = <&mmsys CLK_MM_DISP_AAL>;
834 clocks = <&mmsys CLK_MM_DISP_GAMMA>;
842 clocks = <&mmsys CLK_MM_DISP_MERGE>;
849 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
856 clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
864 clocks = <&mmsys CLK_MM_DISP_UFOE>;
873 clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
874 <&mmsys CLK_MM_DSI0_DIGITAL>,
887 clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
888 <&mmsys CLK_MM_DSI1_DIGITAL>,
901 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
902 <&mmsys CLK_MM_DPI_ENGINE>,
912 clocks = <&mmsys CLK_MM_DISP_PWM026M>, <&mmsys CLK_MM_DISP_PWM0MM>;
921 clocks = <&mmsys CLK_MM_DISP_PWM126M>, <&mmsys CLK_MM_DISP_PWM1MM>;
931 clocks = <&mmsys CLK_MM_MUTEX_32K>;
940 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_LARB0>;
951 clocks = <&infracfg CLK_INFRA_SMI>, <&mmsys CLK_MM_SMI_COMMON>;
958 clocks = <&mmsys CLK_MM_DISP_OD>;
965 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&infracfg CLK_INFRA_SMI>;