Lines Matching full:mmsys
906 <&mmsys CLK_MM_SMI_COMMON>,
907 <&mmsys CLK_MM_SMI_LARB0>,
908 <&mmsys CLK_MM_SMI_LARB1>,
909 <&mmsys CLK_MM_GALS_COMM0>,
910 <&mmsys CLK_MM_GALS_COMM1>,
911 <&mmsys CLK_MM_GALS_CCU2MM>,
912 <&mmsys CLK_MM_GALS_IPU12MM>,
913 <&mmsys CLK_MM_GALS_IMG2MM>,
914 <&mmsys CLK_MM_GALS_CAM2MM>,
915 <&mmsys CLK_MM_GALS_IPU2MM>;
1661 mmsys: syscon@14000000 { label
1662 compatible = "mediatek,mt8183-mmsys", "syscon";
1678 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
1679 <&mmsys CLK_MM_MDP_RSZ1>;
1692 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
1701 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
1711 clocks = <&mmsys CLK_MM_MDP_WROT0>;
1723 clocks = <&mmsys CLK_MM_MDP_WDMA0>;
1732 clocks = <&mmsys CLK_MM_DISP_OVL0>;
1742 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
1752 clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
1762 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1773 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1785 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1794 clocks = <&mmsys CLK_MM_DISP_CCORR0>;
1803 clocks = <&mmsys CLK_MM_DISP_AAL0>;
1812 clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
1821 clocks = <&mmsys CLK_MM_DISP_DITHER0>;
1830 clocks = <&mmsys CLK_MM_DSI0_MM>,
1831 <&mmsys CLK_MM_DSI0_IF>,
1834 resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
1844 clocks = <&mmsys CLK_MM_DPI_IF>,
1845 <&mmsys CLK_MM_DPI_MM>,
1864 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1865 <&mmsys CLK_MM_SMI_LARB0>;
1873 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1874 <&mmsys CLK_MM_SMI_COMMON>,
1875 <&mmsys CLK_MM_GALS_COMM0>,
1876 <&mmsys CLK_MM_GALS_COMM1>;
1887 clocks = <&mmsys CLK_MM_MDP_CCORR>;
1901 <&mmsys CLK_MM_GALS_IMG2MM>;
1911 <&mmsys CLK_MM_GALS_IPU2MM>;
2023 <&mmsys CLK_MM_GALS_CAM2MM>;
2033 <&mmsys CLK_MM_GALS_IPU12MM>;