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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Dmti,gic.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPS Global Interrupt Controller
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
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/linux-6.12.1/drivers/clocksource/
Dmips-gic-timer.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
4 #define pr_fmt(fmt) "mips-gic-timer: " fmt
17 #include <asm/mips-cps.h>
55 int cpu = cpumask_first(evt->cpumask); in gic_next_event()
67 res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0; in gic_next_event()
76 cd->event_handler(cd); in gic_compare_interrupt()
90 cd->name = "MIPS GIC"; in gic_clockevent_cpu_init()
91 cd->features = CLOCK_EVT_FEAT_ONESHOT | in gic_clockevent_cpu_init()
94 cd->rating = 350; in gic_clockevent_cpu_init()
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/linux-6.12.1/arch/mips/mti-malta/
Dmalta-time.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Carsten Langgaard, carstenl@mips.com
4 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
6 * Setting up the clock on the MIPS boards.
28 #include <asm/mc146818-time.h>
30 #include <asm/mips-cps.h>
32 #include <asm/mips-boards/generic.h>
33 #include <asm/mips-boards/maltaint.h>
54 freq -= freq % (amount*2); in freqround()
59 * Estimate CPU and GIC frequencies.
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Dmalta-dtshim.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
15 #include <asm/mips-boards/generic.h>
16 #include <asm/mips-boards/malta.h>
17 #include <asm/mips-cps.h>
91 size -= size_preio; in gen_fdt_mem_array()
99 * obscures 256MB from 0x10000000-0x1fffffff. in gen_fdt_mem_array()
105 size -= SZ_256M; in gen_fdt_mem_array()
115 * obscures 256MB from 0x10000000-0x1fffffff in the low alias in gen_fdt_mem_array()
169 * SOC-it swaps, or perhaps doesn't swap, when DMA'ing in append_memory()
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/linux-6.12.1/drivers/irqchip/
Dirq-mips-gic.c6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
26 #include <asm/mips-cps.h>
30 #include <dt-bindings/interrupt-controller/mips-gic.h>
35 /* Add 2 to convert GIC CPU pin to core interrupt */
38 /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
41 /* Convert between local/shared IRQ number and GIC HW IRQ number. */
44 #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
47 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_IRQCHIP) += irqchip.o
4 obj-$(CONFIG_AL_FIC) += irq-al-fic.o
5 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
6 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
7 obj-$(CONFIG_ATH79) += irq-ath79-misc.o
8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
9 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
10 obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o
11 obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o
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/linux-6.12.1/arch/mips/boot/dts/img/
Dboston.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/boston-clock.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 stdout-path = "uart0:115200";
23 #address-cells = <1>;
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/linux-6.12.1/arch/mips/boot/dts/ralink/
Dmt7621.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 #include <dt-bindings/interrupt-controller/mips-gic.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/clock/mt7621-clk.h>
5 #include <dt-bindings/reset/mt7621-reset.h>
8 compatible = "mediatek,mt7621-soc";
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
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/linux-6.12.1/arch/mips/include/asm/
Dmips-gic.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
16 /* The base address of the GIC registers */
19 /* Offsets from the GIC base address to various control blocks */
29 /* For read-only shared registers */
31 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
32 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
34 /* For read-write shared registers */
36 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
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Dmips-cm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
8 # error Please include asm/mips-cps.h rather than asm/mips-cm.h
21 /* The base address of the CM L2-only sync region */
25 * mips_cm_phys_base - retrieve the physical base address of the CM
36 * mips_cm_l2sync_phys_base - retrieve the physical base address of the CM
37 * L2-sync region
40 * L2-cache only region. It provides a default implementation which reads the
49 * mips_cm_is64 - determine CM register width
54 * or vice-versa. This variable indicates the width of the memory accesses
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/linux-6.12.1/arch/mips/boot/dts/mti/
Dsead3.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "mti,sead-3";
14 model = "MIPS SEAD-3";
17 stdout-path = "serial1:115200";
36 cpu_intc: interrupt-controller {
37 compatible = "mti,cpu-interrupt-controller";
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Dmalta.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/mips-gic.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 cpu_intc: interrupt-controller {
17 compatible = "mti,cpu-interrupt-controller";
19 interrupt-controller;
20 #interrupt-cells = <1>;
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/linux-6.12.1/Documentation/devicetree/bindings/bus/
Dpalmbus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 The ralink palmbus controller can be found in all ralink MIPS
19 pattern: "^palmbus(@[0-9a-f]+)?$"
21 "#address-cells":
24 "#size-cells":
36 # All other properties should be child nodes with unit-address and 'reg'
37 "@[0-9a-f]+$":
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Dbaikal,bt1-axi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
23 accessible by means of the Baikal-T1 System Controller.
26 - $ref: /schemas/simple-bus.yaml#
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/linux-6.12.1/arch/mips/include/asm/mips-boards/
Dmaltaint.h6 * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved.
7 * Carsten Langgaard <carstenl@mips.com>
8 * Steven J. Hill <sjhill@mips.com>
23 #define MIPSCPU_INT_GIC MIPSCPU_INT_MB0 /* GIC chained interrupt */
33 * Interrupts 96..127 are used for Soc-it Classic interrupts
37 /* SOC-it Classic interrupt offsets */
42 * Interrupts 96..127 are used for Soc-it EIC interrupts
46 /* SOC-it EIC interrupt offsets */
Dmalta.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Carsten Langgaard, carstenl@mips.com
4 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
6 * Defines of the Malta board specific address-MAP, registers, etc.
13 #include <asm/mips-boards/msc01_pci.h>
16 /* Mips interrupt controller found in SOCit variations */
49 * GIC Specific definitions
71 * Malta RTC-device indirect register access.
/linux-6.12.1/arch/mips/boot/dts/mobileye/
Deyeq6h.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
6 #include <dt-bindings/interrupt-controller/mips-gic.h>
8 #include "eyeq6h-fixed-clocks.dtsi"
11 #address-cells = <2>;
12 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
28 cpu_intc: interrupt-controller {
29 compatible = "mti,cpu-interrupt-controller";
30 interrupt-controller;
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Deyeq5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
6 #include <dt-bindings/interrupt-controller/mips-gic.h>
8 #include "eyeq5-clocks.dtsi"
11 #address-cells = <2>;
12 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
24 reserved-memory {
25 #address-cells = <2>;
26 #size-cells = <2>;
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/linux-6.12.1/Documentation/devicetree/bindings/gpio/
Dmediatek,mt7621-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/mediatek,mt7621-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
17 using GIC INT12.
21 pattern: "^gpio@[0-9a-f]+$"
24 const: mediatek,mt7621-gpio
29 "#gpio-cells":
32 gpio-controller: true
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/linux-6.12.1/Documentation/devicetree/bindings/net/dsa/
Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
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/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dmediatek,mt7621-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
18 .-------.
22 '-------'
27 .------------------.
28 .-----------| HOST/PCI Bridge |------------.
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/linux-6.12.1/arch/mips/kernel/
Dvdso.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include <asm/mips-cps.h>
26 /* Kernel-provided data used by the VDSO. */
31 * Mapping for the VDSO data/GIC pages. The real pages are mapped manually, as
46 BUG_ON(!PAGE_ALIGNED(image->data)); in init_vdso_image()
47 BUG_ON(!PAGE_ALIGNED(image->size)); in init_vdso_image()
49 num_pages = image->size / PAGE_SIZE; in init_vdso_image()
51 data_pfn = __phys_to_pfn(__pa_symbol(image->data)); in init_vdso_image()
53 image->mapping.pages[i] = pfn_to_page(data_pfn + i); in init_vdso_image()
81 if (current->flags & PF_RANDOMIZE) { in vdso_base()
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/linux-6.12.1/arch/mips/generic/
Dboard-sead3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
17 #include <asm/yamon-dt.h>
56 /* leave the GIC node intact if a GIC is present */ in remove_gic()
61 gic_off = fdt_node_offset_by_compatible(fdt, -1, "mti,gic"); in remove_gic()
63 pr_err("unable to find DT GIC node: %d\n", gic_off); in remove_gic()
69 pr_err("unable to nop GIC node\n"); in remove_gic()
73 cpu_off = fdt_node_offset_by_compatible(fdt, -1, in remove_gic()
74 "mti,cpu-interrupt-controller"); in remove_gic()
83 return -EINVAL; in remove_gic()
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/linux-6.12.1/Documentation/devicetree/bindings/i2c/
Dst,nomadik-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/st,nomadik-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 STn8815. It was part of the prototype STn8500 which then became ST-Ericsson
15 - Linus Walleij <linus.walleij@linaro.org>
23 - st,nomadik-i2c
24 - mobileye,eyeq5-i2c
26 - compatible
31 - items:
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/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dbrcm,bcm63xx-hsspi.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - William Zhang <william.zhang@broadcom.com>
11 - Kursad Oney <kursad.oney@broadcom.com>
12 - Jonas Gorski <jonas.gorski@gmail.com>
16 early MIPS based chips such as BCM6328 and BCM63268. This initial rev 1.0
18 BCM4908 and BCM6858. The old MIPS based chip should continue to use the
19 brcm,bcm6328-hsspi compatible string. The recent ARM based chip is required to
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