dts/mobileye/eyeq5.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
6 #include <dt-bindings/interrupt-controller/mips-gic.h>
8 #include "eyeq5-clocks.dtsi"
11 	#address-cells = <2>;
12 	#size-cells = <2>;
14 		#address-cells = <1>;
15 		#size-cells = <0>;
24 	reserved-memory {
25 		#address-cells = <2>;
26 		#size-cells = <2>;
39 		pci0_msi_reserved: pci0-msi@806000000 {
42 		pci1_msi_reserved: pci1-msi@806100000 {
46 		mini_coredump0_reserved: mini-coredump0@806200000 {
49 		mhm_reserved_0: the-mhm-reserved-0@0 {
60 	cpu_intc: interrupt-controller {
61 		compatible = "mti,cpu-interrupt-controller";
62 		interrupt-controller;
63 		#address-cells = <0>;
64 		#interrupt-cells = <1>;
68 		#address-cells = <2>;
69 		#size-cells = <2>;
71 		compatible = "simple-bus";
76 			reg-io-width = <4>;
77 			interrupt-parent = <&gic>;
80 			clock-names = "uartclk", "apb_pclk";
82 			pinctrl-names = "default";
83 			pinctrl-0 = <&uart0_pins>;
89 			reg-io-width = <4>;
90 			interrupt-parent = <&gic>;
93 			clock-names = "uartclk", "apb_pclk";
95 			pinctrl-names = "default";
96 			pinctrl-0 = <&uart1_pins>;
102 			reg-io-width = <4>;
103 			interrupt-parent = <&gic>;
106 			clock-names = "uartclk", "apb_pclk";
108 			pinctrl-names = "default";
109 			pinctrl-0 = <&uart2_pins>;
112 		olb: system-controller@e00000 {
113 			compatible = "mobileye,eyeq5-olb", "syscon";
115 			#reset-cells = <2>;
116 			#clock-cells = <1>;
118 			clock-names = "ref";
121 		gic: interrupt-controller@140000 {  label
122 			compatible = "mti,gic";
124 			interrupt-controller;
125 			#interrupt-cells = <3>;
128 			* Declare the interrupt-parent even though the mti,gic
133 			interrupt-parent = <&cpu_intc>;
136 				compatible = "mti,gic-timer";
144 #include "eyeq5-pins.dtsi"