bindings/pci/mediatek%2Cmt7621-pcie.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Sergio Paracuellos <sergio.paracuellos@gmail.com>
14   with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
18                                    .-------.
22                                    '-------'
27                               .------------------.
28                   .-----------|  HOST/PCI Bridge |------------.
29                   |           '------------------'            | Type1
32           .-------------.        .-------------.       .-------------.
36           '-------------'        '-------------'       '-------------'
40            .----------.           .----------.          .----------.
43            '----------'           '----------'          '----------'
46   - $ref: /schemas/pci/pci-host-bridge.yaml#
50     const: mediatek,mt7621-pci
54       - description: host-pci bridge registers
55       - description: pcie port 0 RC control registers
56       - description: pcie port 1 RC control registers
57       - description: pcie port 2 RC control registers
63   '^pcie@[0-2],0$':
65     $ref: /schemas/pci/pci-pci-bridge.yaml#
80       phy-names:
81         pattern: '^pcie-phy[0-2]$'
84       - "#interrupt-cells"
85       - interrupt-map-mask
86       - interrupt-map
87       - resets
88       - clocks
89       - phys
90       - phy-names
91       - ranges
96   - compatible
97   - reg
98   - ranges
99   - "#interrupt-cells"
100   - interrupt-map-mask
101   - interrupt-map
102   - reset-gpios
107   - |
108     #include <dt-bindings/gpio/gpio.h>
109     #include <dt-bindings/interrupt-controller/mips-gic.h>
112         compatible = "mediatek,mt7621-pci";
118         #address-cells = <3>;
119         #size-cells = <2>;
120         pinctrl-names = "default";
121         pinctrl-0 = <&pcie_pins>;
125         #interrupt-cells = <1>;
126         interrupt-map-mask = <0xF800 0 0 0>;
127         interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
128                         <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
129                         <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
130         reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
134             #address-cells = <3>;
135             #size-cells = <2>;
137             #interrupt-cells = <1>;
138             interrupt-map-mask = <0 0 0 0>;
139             interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
143             phy-names = "pcie-phy0";
149             #address-cells = <3>;
150             #size-cells = <2>;
152             #interrupt-cells = <1>;
153             interrupt-map-mask = <0 0 0 0>;
154             interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
158             phy-names = "pcie-phy1";
164             #address-cells = <3>;
165             #size-cells = <2>;
167             #interrupt-cells = <1>;
168             interrupt-map-mask = <0 0 0 0>;
169             interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
173             phy-names = "pcie-phy2";