Lines Matching +full:mips +full:- +full:gic
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 #include <dt-bindings/interrupt-controller/mips-gic.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/clock/mt7621-clk.h>
5 #include <dt-bindings/reset/mt7621-reset.h>
8 compatible = "mediatek,mt7621-soc";
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "mips,mips1004Kc";
24 compatible = "mips,mips1004Kc";
31 compatible = "mti,cpu-interrupt-controller";
33 #address-cells = <0>;
34 #interrupt-cells = <1>;
36 interrupt-controller;
39 mmc_fixed_3v3: regulator-3v3 {
40 compatible = "regulator-fixed";
42 enable-active-high;
44 regulator-always-on;
45 regulator-max-microvolt = <3300000>;
46 regulator-min-microvolt = <3300000>;
47 regulator-name = "mmc_power";
50 mmc_fixed_1v8_io: regulator-1v8 {
51 compatible = "regulator-fixed";
53 enable-active-high;
55 regulator-always-on;
56 regulator-max-microvolt = <1800000>;
57 regulator-min-microvolt = <1800000>;
58 regulator-name = "mmc_io";
62 compatible = "ralink,mt7621-pinctrl";
64 i2c_pins: i2c0-pins {
71 mdio_pins: mdio0-pins {
78 nand_pins: nand0-pins {
79 sdhci-pinmux {
84 spi-pinmux {
90 pcie_pins: pcie0-pins {
97 rgmii1_pins: rgmii1-pins {
104 rgmii2_pins: rgmii2-pins {
111 sdhci_pins: sdhci0-pins {
118 spi_pins: spi0-pins {
125 uart1_pins: uart1-pins {
132 uart2_pins: uart2-pins {
139 uart3_pins: uart3-pins {
152 #address-cells = <1>;
153 #size-cells = <1>;
156 compatible = "mediatek,mt7621-sysc", "syscon";
159 #clock-cells = <1>;
160 #reset-cells = <1>;
162 clock-output-names = "xtal", "cpu", "bus",
170 compatible = "mediatek,mt7621-wdt";
176 compatible = "mediatek,mt7621-gpio";
179 #gpio-cells = <2>;
180 #interrupt-cells = <2>;
182 gpio-controller;
183 gpio-ranges = <&pinctrl 0 0 95>;
185 interrupt-controller;
186 interrupt-parent = <&gic>;
191 compatible = "mediatek,mt7621-i2c";
194 #address-cells = <1>;
195 #size-cells = <0>;
198 clock-names = "i2c";
200 pinctrl-names = "default";
201 pinctrl-0 = <&i2c_pins>;
204 reset-names = "i2c";
209 memc: memory-controller@5000 {
210 compatible = "mediatek,mt7621-memc", "syscon";
218 reg-io-width = <4>;
219 reg-shift = <2>;
223 interrupt-parent = <&gic>;
226 no-loopback-test;
228 pinctrl-names = "default";
229 pinctrl-0 = <&uart1_pins>;
236 reg-io-width = <4>;
237 reg-shift = <2>;
241 interrupt-parent = <&gic>;
244 no-loopback-test;
246 pinctrl-names = "default";
247 pinctrl-0 = <&uart2_pins>;
256 reg-io-width = <4>;
257 reg-shift = <2>;
261 interrupt-parent = <&gic>;
264 no-loopback-test;
266 pinctrl-names = "default";
267 pinctrl-0 = <&uart3_pins>;
273 compatible = "ralink,mt7621-spi";
276 #address-cells = <1>;
277 #size-cells = <0>;
279 clock-names = "spi";
282 pinctrl-names = "default";
283 pinctrl-0 = <&spi_pins>;
285 reset-names = "spi";
293 compatible = "mediatek,mt7620-mmc";
296 bus-width = <4>;
298 cap-mmc-highspeed;
299 cap-sd-highspeed;
303 clock-names = "source", "hclk";
305 disable-wp;
307 interrupt-parent = <&gic>;
310 max-frequency = <48000000>;
312 pinctrl-names = "default", "state_uhs";
313 pinctrl-0 = <&sdhci_pins>;
314 pinctrl-1 = <&sdhci_pins>;
316 vmmc-supply = <&mmc_fixed_3v3>;
317 vqmmc-supply = <&mmc_fixed_1v8_io>;
323 compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
326 reg-names = "mac", "ippc";
328 #address-cells = <1>;
329 #size-cells = <0>;
332 clock-names = "sys_ck";
334 interrupt-parent = <&gic>;
338 gic: interrupt-controller@1fbc0000 { label
339 compatible = "mti,gic";
342 #interrupt-cells = <3>;
343 interrupt-controller;
345 mti,reserved-cpu-vectors = <7>;
348 compatible = "mti,gic-timer";
355 compatible = "mti,mips-cpc";
360 compatible = "mti,mips-cdmm";
365 compatible = "mediatek,mt7621-eth";
368 #address-cells = <1>;
369 #size-cells = <0>;
371 clock-names = "fe", "ethif";
374 interrupt-parent = <&gic>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
380 reset-names = "fe", "eth";
385 mdio: mdio-bus {
386 #address-cells = <1>;
387 #size-cells = <0>;
393 #interrupt-cells = <1>;
394 interrupt-controller;
397 reset-names = "mcm";
403 #address-cells = <1>;
404 #size-cells = <0>;
440 phy-mode = "rgmii";
442 fixed-link {
443 full-duplex;
453 phy-mode = "trgmii";
455 fixed-link {
456 full-duplex;
466 compatible = "mediatek,eth-mac";
469 phy-mode = "trgmii";
471 fixed-link {
472 full-duplex;
479 compatible = "mediatek,eth-mac";
482 phy-mode = "rgmii";
484 fixed-link {
485 full-duplex;
494 compatible = "mediatek,mt7621-pci";
495 reg = <0x1e140000 0x100>, /* host-pci bridge registers */
502 #address-cells = <3>;
503 #interrupt-cells = <1>;
504 #size-cells = <2>;
508 interrupt-map-mask = <0xf800 0 0 0>;
509 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
510 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
511 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
513 pinctrl-names = "default";
514 pinctrl-0 = <&pcie_pins>;
516 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
524 #address-cells = <3>;
525 #interrupt-cells = <1>;
526 #size-cells = <2>;
532 interrupt-map-mask = <0 0 0 0>;
533 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
535 phy-names = "pcie-phy0";
545 #address-cells = <3>;
546 #interrupt-cells = <1>;
547 #size-cells = <2>;
553 interrupt-map-mask = <0 0 0 0>;
554 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
556 phy-names = "pcie-phy1";
566 #address-cells = <3>;
567 #interrupt-cells = <1>;
568 #size-cells = <2>;
574 interrupt-map-mask = <0 0 0 0>;
575 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
577 phy-names = "pcie-phy2";
584 pcie0_phy: pcie-phy@1e149000 {
585 compatible = "mediatek,mt7621-pci-phy";
588 #phy-cells = <1>;
593 pcie2_phy: pcie-phy@1e14a000 {
594 compatible = "mediatek,mt7621-pci-phy";
597 #phy-cells = <1>;