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/linux-6.12.1/Documentation/core-api/irq/
Dirq-domain.rst2 The irq_domain interrupt number mapping library
7 This is simple when there is only one interrupt controller, but in
8 systems with multiple interrupt controllers the kernel must ensure
9 that each one gets assigned non-overlapping allocations of Linux
12 The number of interrupt controllers registered as unique irqchips
15 mechanisms as the IRQ core system by modelling their interrupt
16 handlers as irqchips, i.e. in effect cascading interrupt controllers.
18 Here the interrupt number loose all kind of correspondence to
19 hardware interrupt numbers: whereas in the past, IRQ numbers could
21 interrupt controller (i.e. the component actually fireing the
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/linux-6.12.1/Documentation/devicetree/bindings/pci/
Drockchip-dw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe Root Complex controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
15 RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
17 snps,dw-pcie.yaml.
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Dxlnx,nwl-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: xlnx,nwl-pcie-2.11
22 - description: PCIe bridge registers location.
23 - description: PCIe Controller registers location.
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Drockchip,rk3399-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
24 - const: axi-base
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Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
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Drockchip-dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe RC/EP controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
15 Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip
22 - description: AHB clock for PCIe master
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Daardvark-pci.txt1 Aardvark PCIe controller
3 This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
5 The Device Tree node describing an Aardvark PCIe controller must
8 - compatible: Should be "marvell,armada-3700-pcie"
9 - reg: range of registers for the PCIe controller
10 - interrupts: the interrupt line of the PCIe controller
11 - #address-cells: set to <3>
12 - #size-cells: set to <2>
13 - device_type: set to "pci"
14 - ranges: ranges for the PCI memory and I/O regions
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/linux-6.12.1/Documentation/PCI/
Dboot-interrupts.rst1 .. SPDX-License-Identifier: GPL-2.0
7 :Author: - Sean V Kelley <sean.v.kelley@linux.intel.com>
13 interrupt messages (Assert_INTx/Deassert_INTx). The integrated IO-APIC in a
14 given Core IO converts the legacy interrupt messages from PCI Express to
15 MSI interrupts. If the IO-APIC is disabled (via the mask bits in the
16 IO-APIC table entries), the messages are routed to the legacy PCH. This
17 in-band interrupt mechanism was traditionally necessary for systems that
18 did not support the IO-APIC and for boot. Intel in the past has used the
20 protocol describes this in-band legacy wire-interrupt INTx mechanism for
21 I/O devices to signal PCI-style level interrupts. The subsequent paragraphs
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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Dnvidia,tegra20-ictlr.txt1 NVIDIA Legacy Interrupt Controller
3 All Tegra SoCs contain a legacy interrupt controller that routes
7 The HW block exposes a number of interrupt controllers, each
12 - compatible : should be: "nvidia,tegra<chip>-ictlr". The LIC on
13 subsequent SoCs remained backwards-compatible with Tegra30, so on
15 include "nvidia,tegra30-ictlr".
16 - reg : Specifies base physical address and size of the registers.
17 Each controller must be described separately (Tegra20 has 4 of them,
19 - interrupt-controller : Identifies the node as an interrupt controller.
20 - #interrupt-cells : Specifies the number of cells needed to encode an
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Daspeed,ast2400-vic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2400-vic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Aspeed Vectored Interrupt Controller
10 - Andrew Jeffery <andrew@codeconstruct.com.au>
13 The AST2400 and AST2500 SoC families include a legacy register layout before
20 - aspeed,ast2400-vic
21 - aspeed,ast2500-vic
26 interrupt-controller: true
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Dmstar,mst-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MStar Interrupt Controller
10 - Mark-PK Tsai <mark-pk.tsai@mediatek.com>
13 MStar, SigmaStar and Mediatek TV SoCs contain multiple legacy
14 interrupt controllers that routes interrupts to the GIC.
16 The HW block exposes a number of interrupt controllers, each
21 const: mstar,mst-intc
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Dintel,ce4100-lapic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Local Advanced Programmable Interrupt Controller (LAPIC)
10 - Rahul Tanwar <rtanwar@maxlinear.com>
13 Intel's Advanced Programmable Interrupt Controller (APIC) is a
14 family of interrupt controllers. The APIC is a split
17 (lapic) receives interrupts from the processor's interrupt pins,
26 This schema defines bindings for local APIC interrupt controller.
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/linux-6.12.1/arch/x86/include/asm/
Dx86_init.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 * struct x86_init_mpparse - platform specific mpparse ops
28 * struct x86_init_resources - platform specific resource related ops
43 * struct x86_init_irqs - platform specific interrupt setup
44 * @pre_vector_init: init code to run before interrupt vectors
46 * @intr_init: interrupt init code
47 * @intr_mode_select: interrupt delivery mode selection
48 * @intr_mode_init: interrupt delivery mode setup
49 * @create_pci_msi_domain: Create the PCI/MSI interrupt domain
60 * struct x86_init_oem - oem platform specific customizing functions
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/linux-6.12.1/arch/powerpc/sysdev/
Di8259.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * i8259 interrupt controller driver.
8 #include <linux/interrupt.h>
26 * Acknowledge the IRQ using either the PCI host bridge's interrupt
29 * IBM and Motorola PReP boxes so we must use the int-ack feature on them.
36 /* Either int-ack or poll for the IRQ */ in i8259_irq()
43 /* Perform an interrupt acknowledge cycle on controller 1. */ in i8259_irq()
48 * Interrupt is cascaded so perform interrupt in i8259_irq()
49 * acknowledge on controller 2. in i8259_irq()
58 * This may be a spurious interrupt. in i8259_irq()
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/linux-6.12.1/Documentation/devicetree/bindings/gpio/
Dti,omap-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/ti,omap-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: OMAP GPIO controller
10 - Grygorii Strashko <grygorii.strashko@ti.com>
13 The general-purpose interface combines general-purpose input/output (GPIO) banks.
14 Each GPIO banks provides up to 32 dedicated general-purpose pins with input
15 and output capabilities; interrupt generation in active mode and wake-up
21 - enum:
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/linux-6.12.1/Documentation/arch/loongarch/
Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
9 Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
17 and there are two models of hierarchy (legacy model and extended model).
19 Legacy IRQ model
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/linux-6.12.1/arch/parisc/include/asm/
Dsuperio.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define SIO_FDCBAR 0x90 /* Floppy Disk Controller BAR */
19 /* Interrupt Routing Control registers */
30 #define CFG_IR_LOW CFG_IR_SER /* Lowest interrupt routing reg */
31 #define CFG_IR_HIGH CFG_IR_ACPI /* Highest interrupt routing reg */
34 #define OCW2_EOI 0x20 /* Non-specific EOI */
38 #define OCW3_POLL 0x0C /* Poll the PIC for an interrupt vector */
40 /* Interrupt lines. Only PIC1 is used */
45 #define FDC_IRQ 6 /* Floppy controller */
60 struct pci_dev *lio_pdev; /* pci device for legacy IO (fn 1) */
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/linux-6.12.1/arch/powerpc/boot/dts/
Dcurrituck.dts11 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
37 d-cache-line-size = <32>;
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Dredwood.dts11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
26 #address-cells = <1>;
27 #size-cells = <0>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
35 i-cache-line-size = <32>;
36 d-cache-line-size = <32>;
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Dakebono.dts12 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <1600000000>; // 1.6 GHz
36 timebase-frequency = <100000000>; // 100Mhz
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
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/linux-6.12.1/drivers/parisc/
Dsuperio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* National Semiconductor NS87560UBD Super I/O controller used in
14 * (C) Copyright 2003 Grant Grundler <grundler parisc-linux org>
15 * (C) Copyright 2005 Kyle McMartin <kyle@parisc-linux.org>
21 * Major changes to get basic interrupt infrastructure working to
23 * works with serial. -- John Marvin <jsm@fc.hp.com>
26 * -- Kyle McMartin <kyle@parisc-linux.org>
32 * Function 0 is an IDE controller. It is identical to a PC87415 IDE
33 * controller (and identifies itself as such).
35 * Function 1 is a "Legacy I/O" controller. Under this function is a
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/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/
Dti,gpmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments GPMC Memory Controller
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
14 The GPMC is a unified memory controller dedicated for interfacing
16 - Asynchronous SRAM-like memories and ASICs
17 - Asynchronous, synchronous, and page mode burst NOR flash
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/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3588-extra.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk3588-base.dtsi"
7 #include "rk3588-extra-pinctrl.dtsi"
11 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
16 clock-names = "ref_clk", "suspend_clk", "bus_clk";
19 phy-names = "usb2-phy", "usb3-phy";
21 power-domains = <&power RK3588_PD_USB>;
24 snps,dis-u2-freeclk-exists-quirk;
25 snps,dis-del-phy-power-chg-quirk;
26 snps,dis-tx-ipgap-linecheck-quirk;
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Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
16 clock-names = "sata", "pmalive", "rxoob";
19 phy-names = "sata-phy";
20 ports-implemented = <0x1>;
21 power-domains = <&power RK3568_PD_PIPE>;
26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
31 compatible = "rockchip,rk3568-qos", "syscon";
36 compatible = "rockchip,rk3568-qos", "syscon";
41 compatible = "rockchip,rk3568-qos", "syscon";
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/linux-6.12.1/Documentation/devicetree/bindings/mmc/
Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI AM654 MMC Controller
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
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