Documentation/PCI/boot-interrupts.rst

1 .. SPDX-License-Identifier: GPL-2.0
7 :Author: - Sean V Kelley <sean.v.kelley@linux.intel.com>
13 interrupt messages (Assert_INTx/Deassert_INTx). The integrated IO-APIC in a
14 given Core IO converts the legacy interrupt messages from PCI Express to
15 MSI interrupts.  If the IO-APIC is disabled (via the mask bits in the
16 IO-APIC table entries), the messages are routed to the legacy PCH. This
17 in-band interrupt mechanism was traditionally necessary for systems that
18 did not support the IO-APIC and for boot. Intel in the past has used the
20 protocol describes this in-band legacy wire-interrupt INTx mechanism for
21 I/O devices to signal PCI-style level interrupts. The subsequent paragraphs
29 When in-band legacy INTx messages are forwarded to the PCH, they in turn
30 trigger a new interrupt for which the OS likely lacks a handler. When an
31 interrupt goes unhandled over time, they are tracked by the Linux kernel as
34 now prevents valid usage by an existing interrupt which may happen to share
38   CPU: 0 PID: 2988 Comm: irq/34-nipalk Tainted: 4.14.87-rt49-02410-g4a640ec-dirty #1
39   Hardware name: National Instruments NI PXIe-8880/NI PXIe-8880, BIOS 2.1.5f1 01/09/2020
64 this problem today. Threaded interrupts may not be re-enabled after the IRQ
65 handler wakes. These "one shot" conditions mean that the threaded interrupt
66 needs to keep the interrupt line masked until the threaded handler has run.
69 since the interrupt of the issuing device is still active.
74 The legacy interrupt forwarding mechanism exists today in a number of
79 Starting with ICX there are no longer any IO-APICs in the Core IO's
80 devices.  IO-APIC is only in the PCH.  Devices connected to the Core IO's
81 PCIe Root Ports will use native MSI/MSI-X mechanisms.
88 In such a case a quirk to disable boot interrupt generation can be
91 Intel® 6300ESB I/O Controller Hub
93    BIE: Boot Interrupt Enable
96 	  0   Boot interrupt is enabled.
97 	  1   Boot interrupt is disabled.
101   Coherent Interface Protocol Interrupt Control
104 	  Intel® Quick Data DMA/PCI Express ports are not routed to legacy
105 	  PCH - they are either converted into MSI via the integrated IO-APIC
106 	  (if the IO-APIC mask bit is clear in the appropriate entries)
110 has been to make use of PCI Interrupt pin to INTx routing tables for
111 purposes of redirecting the interrupt handler to the rerouted interrupt
113 disabled, the Linux kernel will reroute the valid interrupt to its legacy
114 interrupt. This redirection of the handler will prevent the occurrence of
115 the spurious interrupt detection which would ordinarily disable the IRQ
119 disable) the redirection of the interrupt handler to the PCH interrupt
127 There is an overview of the legacy interrupt handling in several datasheets
131 Example of disabling of the boot interrupt
132 ------------------------------------------
134       - Intel® 6300ESB I/O Controller Hub (Document # 300641-004US)
135 	5.7.3 Boot Interrupt
136 	https://www.intel.com/content/dam/doc/datasheet/6300esb-io-controller-hub-datasheet.pdf
138       - Intel® Xeon® Processor E5-1600/2400/2600/4600 v3 Product Families
139 	Datasheet - Volume 2: Registers (Document # 330784-003)
140 	6.6.41 cipintrc Coherent Interface Protocol Interrupt Control
141 …https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e5-v3-datasheet-vol-2…
144 ----------------------------
146       - Intel® 6700PXH 64-bit PCI Hub (Document # 302628)
147 	2.15.2 PCI Express Legacy INTx Support and Boot Interrupt
148 	https://www.intel.com/content/dam/doc/datasheet/6700pxh-64-bit-pci-hub-datasheet.pdf
151 If you have any legacy PCI interrupt questions that aren't answered, email me.
157 .. [1] https://lore.kernel.org/r/12131949181903-git-send-email-sassmann@suse.de/
158 .. [2] https://lore.kernel.org/r/12131949182094-git-send-email-sassmann@suse.de/