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/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Damdgpu_irq.c30 * DOC: Interrupt Handling
32 * Interrupts generated within GPU hardware raise interrupt requests that are
34 * type of the interrupt and dispatching matching handlers. If handling an
35 * interrupt requires calling kernel functions that may sleep processing is
41 * For GPU interrupt sources that may be driven by another driver, IRQ domain
118 * amdgpu_irq_disable_all - disable *all* interrupts
130 spin_lock_irqsave(&adev->irq.lock, irqflags); in amdgpu_irq_disable_all()
132 if (!adev->irq.client[i].sources) in amdgpu_irq_disable_all()
136 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; in amdgpu_irq_disable_all() local
138 if (!src || !src->funcs->set || !src->num_types) in amdgpu_irq_disable_all()
[all …]
/linux-6.12.1/arch/arm/boot/dts/st/
Dste-nomadik-stn8815.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC
6 #include <dt-bindings/gpio/gpio.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
18 L2: cache-controller {
19 compatible = "arm,l210-cache";
21 interrupt-parent = <&vica>;
23 cache-unified;
24 cache-level = <2>;
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_irq.c46 * What DM provides on top are two IRQ tables specifically for top-half and
47 * bottom-half IRQ handling, with the bottom-half implementing workqueues:
49 * - &amdgpu_display_manager.irq_handler_list_high_tab
50 * - &amdgpu_display_manager.irq_handler_list_low_tab
59 * To expose DC's hardware interrupt toggle to the base driver, DM implements
61 * amdgpu_irq_update() to enable or disable the interrupt.
69 * struct amdgpu_dm_irq_handler_data - Data for DM interrupt handlers.
75 * @irq_source: DC interrupt source that this handler is registered for
84 /* DAL irq source which registered for this interrupt. */
90 spin_lock_irqsave(&adev->dm.irq_handler_list_table_lock, flags)
[all …]
/linux-6.12.1/arch/powerpc/platforms/44x/
Duic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * IBM PowerPC 4xx Universal Interrupt Controller
20 #include <linux/interrupt.h>
55 unsigned int src = irqd_to_hwirq(d); in uic_unmask_irq() local
59 sr = 1 << (31-src); in uic_unmask_irq()
60 raw_spin_lock_irqsave(&uic->lock, flags); in uic_unmask_irq()
61 /* ack level-triggered interrupts here */ in uic_unmask_irq()
63 mtdcr(uic->dcrbase + UIC_SR, sr); in uic_unmask_irq()
64 er = mfdcr(uic->dcrbase + UIC_ER); in uic_unmask_irq()
66 mtdcr(uic->dcrbase + UIC_ER, er); in uic_unmask_irq()
[all …]
/linux-6.12.1/arch/powerpc/sysdev/
Dehv_pic.c4 * Copyright 2008-2011 Freescale Semiconductor, Inc.
19 #include <linux/interrupt.h>
47 unsigned int src = virq_to_hw(d->irq); in ehv_pic_unmask_irq() local
49 ev_int_set_mask(src, 0); in ehv_pic_unmask_irq()
54 unsigned int src = virq_to_hw(d->irq); in ehv_pic_mask_irq() local
56 ev_int_set_mask(src, 1); in ehv_pic_mask_irq()
61 unsigned int src = virq_to_hw(d->irq); in ehv_pic_end_irq() local
63 ev_int_eoi(src); in ehv_pic_end_irq()
74 unsigned int src = virq_to_hw(d->irq); in ehv_pic_set_affinity() local
80 ev_int_get_config(src, &config, &prio, &cpu_dest); in ehv_pic_set_affinity()
[all …]
Dcpm2_pic.c9 * 1999-2001 (c) Dan Malek <dan@embeddedalley.com>
17 /* The CPM2 internal interrupt controller. It is usually
18 * the only interrupt controller.
19 * There are two 32-bit registers (high/low) for up to 64
22 * Now, the fun starts.....Interrupt Numbers DO NOT MAP
24 * That is, interrupt 4 does not map to bit position 4.
51 static unsigned long ppc_cached_irq_mask[2]; /* 2 32-bit registers */
86 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); in cpm2_mask_irq()
98 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); in cpm2_unmask_irq()
109 out_be32(&cpm2_intctl->ic_sipnrh + word, 1 << bit); in cpm2_ack()
[all …]
Dfsl_mpic_err.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/interrupt.h>
37 unsigned int src = virq_to_hw(d->irq) - mpic->err_int_vecs[0]; in fsl_mpic_mask_err() local
39 eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR); in fsl_mpic_mask_err()
40 eimr |= (1 << (31 - src)); in fsl_mpic_mask_err()
41 mpic_fsl_err_write(mpic->err_regs, eimr); in fsl_mpic_mask_err()
48 unsigned int src = virq_to_hw(d->irq) - mpic->err_int_vecs[0]; in fsl_mpic_unmask_err() local
50 eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR); in fsl_mpic_unmask_err()
51 eimr &= ~(1 << (31 - src)); in fsl_mpic_unmask_err()
52 mpic_fsl_err_write(mpic->err_regs, eimr); in fsl_mpic_unmask_err()
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Dmpic.c4 * Driver for interrupt controllers following the OpenPIC standard, the
9 * Copyright 2010-2012 Freescale Semiconductor, Inc.
26 #include <linux/interrupt.h>
152 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
164 if (!(mpic->flags & MPIC_SECONDARY)) in mpic_processor_id()
182 return dcr_read(rb->dhost, reg); in _mpic_read()
185 return in_be32(rb->base + (reg >> 2)); in _mpic_read()
188 return in_le32(rb->base + (reg >> 2)); in _mpic_read()
199 dcr_write(rb->dhost, reg, value); in _mpic_write()
203 out_be32(rb->base + (reg >> 2), value); in _mpic_write()
[all …]
/linux-6.12.1/arch/powerpc/platforms/powermac/
Dpic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for the interrupt controllers found on Power Macintosh,
4 * currently Apple's "Grand Central" interrupt controller in all
18 #include <linux/interrupt.h>
30 #include <asm/pci-bridge.h>
61 static int pmac_irq_cascade = -1;
79 unsigned int src = irqd_to_hwirq(d); in pmac_mask_and_ack_irq() local
80 unsigned long bit = 1UL << (src & 0x1f); in pmac_mask_and_ack_irq()
81 int i = src >> 5; in pmac_mask_and_ack_irq()
85 __clear_bit(src, ppc_cached_irq_mask); in pmac_mask_and_ack_irq()
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/linux-6.12.1/arch/arm/boot/dts/renesas/
Dr8a7778.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M1A (R8A77781) SoC
14 #include <dt-bindings/clock/r8a7778-clock.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
20 interrupt-parent = <&gic>;
21 #address-cells = <1>;
22 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
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Dr8a7793.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M2-N (R8A77930) SoC
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/power/r8a7793-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
37 compatible = "fixed-clock";
[all …]
/linux-6.12.1/drivers/comedi/drivers/
Damplc_dio200_common.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
9 * COMEDI - Linux Control and Measurement Device Interface
14 #include <linux/interrupt.h>
26 #define DIO200_INT_SCE 0x1e /* Interrupt enable/status register */
37 * 'which' is: 0 for CTR-X1, CTR-Y1, CTR-Z1; 1 for CTR-X2, CTR-Y2 or CTR-Z2.
94 if (dev->mmio) in dio200___read8()
95 return readb(dev->mmio + offset); in dio200___read8()
96 return inb(dev->iobase + offset); in dio200___read8()
102 if (dev->mmio) in dio200___write8()
[all …]
/linux-6.12.1/arch/powerpc/kvm/
Dmpic.c63 #define OPENPIC_CPU_REG_SIZE (0x100 + ((MAX_CPU - 1) * 0x1000))
116 struct kvm_vcpu *vcpu = current->thread.kvm_vcpu; in get_current_cpu()
117 return vcpu ? vcpu->arch.irq_cpu_id : -1; in get_current_cpu()
120 return -1; in get_current_cpu()
133 IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
134 IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */
154 bool level:1; /* level-triggered */
171 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
175 #define IDR_CI 0x40000000 /* critical interrupt */
184 /* Count of IRQ sources asserting on non-INT outputs */
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Dbook3s_xics.c1 // SPDX-License-Identifier: GPL-2.0-only
40 * sources and avoiding simultaneous deliveries of the same interrupt.
50 * - To speed up resends, keep a bitmap of "resend" set bits in the
53 * - Speed up server# -> ICP lookup (array ? hash table ?)
55 * - Make ICS lockless as well, or at least a per-interrupt lock or hashed
59 /* -- ICS routines -- */
65 * Return value ideally indicates how the interrupt was handled, but no
73 u16 src; in ics_deliver_irq() local
78 ics = kvmppc_xics_find_ics(xics, irq, &src); in ics_deliver_irq()
81 return -EINVAL; in ics_deliver_irq()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Deverest,es8326.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Yang <yangxiaohua@everest-semi.com>
21 - description: clock for master clock (MCLK)
23 clock-names:
25 - const: mclk
27 "#sound-dai-cells":
30 everest,jack-pol:
40 everest,mic1-src:
[all …]
/linux-6.12.1/drivers/dma/
Dste_dma40_ll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2007-2010
4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
31 u32 l1 = 0; /* src */ in d40_log_cfg()
33 /* src is mem? -> increase address pos */ in d40_log_cfg()
34 if (cfg->dir == DMA_MEM_TO_DEV || in d40_log_cfg()
35 cfg->dir == DMA_MEM_TO_MEM) in d40_log_cfg()
38 /* dst is mem? -> increase address pos */ in d40_log_cfg()
39 if (cfg->dir == DMA_DEV_TO_MEM || in d40_log_cfg()
[all …]
/linux-6.12.1/drivers/edac/
Dxgene_edac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * APM X-Gene SoC EDAC (error detection and correction)
12 #include <linux/interrupt.h>
68 *val = readl(edac->pcp_csr + reg); in xgene_edac_pcp_rd()
76 spin_lock(&edac->lock); in xgene_edac_pcp_clrbits()
77 val = readl(edac->pcp_csr + reg); in xgene_edac_pcp_clrbits()
79 writel(val, edac->pcp_csr + reg); in xgene_edac_pcp_clrbits()
80 spin_unlock(&edac->lock); in xgene_edac_pcp_clrbits()
88 spin_lock(&edac->lock); in xgene_edac_pcp_setbits()
89 val = readl(edac->pcp_csr + reg); in xgene_edac_pcp_setbits()
[all …]
/linux-6.12.1/drivers/soc/fsl/qe/
Dqe_ic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * QUICC ENGINE Interrupt Controller
62 * QE interrupt controller internal structure
72 * For grouped interrupts sources - the interrupt code as
248 unsigned int src = irqd_to_hwirq(d); in qe_ic_unmask_irq() local
254 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg); in qe_ic_unmask_irq()
255 qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg, in qe_ic_unmask_irq()
256 temp | qe_ic_info[src].mask); in qe_ic_unmask_irq()
264 unsigned int src = irqd_to_hwirq(d); in qe_ic_mask_irq() local
270 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg); in qe_ic_mask_irq()
[all …]
/linux-6.12.1/drivers/media/platform/samsung/s5p-g2d/
Dg2d-regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Samsung S5P G2D - 2D Graphics Accelerator Driver
11 #define INTEN_REG 0x0004 /* Interrupt Enable reg */
12 #define INTC_PEND_REG 0x000C /* Interrupt Control Pending reg */
24 #define SRC_MSK_DIRECT_REG 0x0204 /* Src and Mask Direction reg */
27 /* Parameter Setting Registers (Src) */
28 #define SRC_SELECT_REG 0x0300 /* Src Image Selection reg */
29 #define SRC_BASE_ADDR_REG 0x0304 /* Src Image Base Address reg */
30 #define SRC_STRIDE_REG 0x0308 /* Src Stride reg */
31 #define SRC_COLOR_MODE_REG 0x030C /* Src Image Color Mode reg */
[all …]
/linux-6.12.1/arch/powerpc/platforms/cell/
Dspider-pic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * External Interrupt Controller on Spider South Bridge
10 #include <linux/interrupt.h>
19 #include "interrupt.h"
21 /* register layout taken from Spider spec, table 7.4-4 */
65 unsigned int src) in spider_get_irq_config() argument
67 return pic->regs + TIR_CFGA + 8 * src; in spider_get_irq_config()
89 unsigned int src = irqd_to_hwirq(d); in spider_ack_irq() local
97 if (src < 47 || src > 50) in spider_ack_irq()
101 out_be32(pic->regs + TIR_EDC, 0x100 | (src & 0xf)); in spider_ack_irq()
[all …]
/linux-6.12.1/arch/m68k/include/asm/
Dmcfdma.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfdma.h -- Coldfire internal DMA support defines.
28 #define MCFDMA_DIVR 0x14 /* DMA interrupt vec (r/w) */
48 #define MCFDMA_DCR_SSIZE_MASK 0x0030 /* Src xfer size */
49 #define MCFDMA_DCR_SSIZE_LONG 0x0000 /* Src xfer size, 00 = longw */
50 #define MCFDMA_DCR_SSIZE_BYTE 0x0010 /* Src xfer size, 01 = byte */
51 #define MCFDMA_DCR_SSIZE_WORD 0x0020 /* Src xfer size, 10 = word */
52 #define MCFDMA_DCR_SSIZE_LINE 0x0030 /* Src xfer size, 11 = line */
74 #define MCFDMA_DIR 0x03 /* Interrupt trigger register (r/w) */
109 /* Bit definitions for the DMA interrupt register (DIR) */
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/reset/
Dfsl,imx-src.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/fsl,imx-src.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Philipp Zabel <p.zabel@pengutronix.de>
15 nodes should specify the reset line on the SRC in their resets
16 property, containing a phandle to the SRC device node and a
31 - const: fsl,imx51-src
32 - items:
33 - enum:
[all …]
/linux-6.12.1/drivers/pinctrl/
Dpinctrl-keembay.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/interrupt.h>
12 #include <linux/pinctrl/pinconf-generic.h>
28 /* GPIO Interrupt and mode registers' offsets */
61 * struct keembay_mux_desc - Mux properties of each GPIO pin
83 * struct keembay_gpio_irq - Config of each GPIO Interrupt sources
84 * @source: Interrupt source number (0 - 7)
85 * @line: Actual Interrupt line number
86 * @pins: Array of GPIO pins using this Interrupt line
87 * @trigger: Interrupt trigger type for this line
[all …]
/linux-6.12.1/Documentation/networking/device_drivers/ethernet/aquantia/
Datlantic.rst1 .. SPDX-License-Identifier: GPL-2.0
8 For the aQuantia Multi-Gigabit PCI Express Family of Ethernet Adapters
12 - Identifying Your Adapter
13 - Configuration
14 - Supported ethtool options
15 - Command Line Parameters
16 - Config file parameters
17 - Support
18 - License
23 The driver in this release is compatible with AQC-100, AQC-107, AQC-108
[all …]
/linux-6.12.1/Documentation/virt/kvm/devices/
Dmpic.rst1 .. SPDX-License-Identifier: GPL-2.0
4 MPIC interrupt controller
9 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0
10 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2
13 MPIC will act as the system interrupt controller, connecting to each
14 vcpu's interrupt inputs.
20 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
25 KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
28 must be 4-byte aligned.
33 KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
[all …]

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