Lines Matching +full:interrupt +full:- +full:src
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * APM X-Gene SoC EDAC (error detection and correction)
12 #include <linux/interrupt.h>
68 *val = readl(edac->pcp_csr + reg); in xgene_edac_pcp_rd()
76 spin_lock(&edac->lock); in xgene_edac_pcp_clrbits()
77 val = readl(edac->pcp_csr + reg); in xgene_edac_pcp_clrbits()
79 writel(val, edac->pcp_csr + reg); in xgene_edac_pcp_clrbits()
80 spin_unlock(&edac->lock); in xgene_edac_pcp_clrbits()
88 spin_lock(&edac->lock); in xgene_edac_pcp_setbits()
89 val = readl(edac->pcp_csr + reg); in xgene_edac_pcp_setbits()
91 writel(val, edac->pcp_csr + reg); in xgene_edac_pcp_setbits()
92 spin_unlock(&edac->lock); in xgene_edac_pcp_setbits()
115 #define MCU_EBLRR_ERRBANK_RD(src) (((src) & 0x00000007) >> 0) argument
117 #define MCU_ERCRR_ERRROW_RD(src) (((src) & 0xFFFF0000) >> 16) argument
118 #define MCU_ERCRR_ERRCOL_RD(src) ((src) & 0x00000FFF) argument
120 #define MCU_SBECNT_COUNT(src) ((src) & 0xFFFF) argument
144 struct mem_ctl_info *mci = file->private_data; in xgene_edac_mc_err_inject_write()
145 struct xgene_edac_mc_ctx *ctx = mci->pvt_info; in xgene_edac_mc_err_inject_write()
151 ctx->mcu_csr + MCUESRRA0 + i * MCU_RANK_STRIDE); in xgene_edac_mc_err_inject_write()
167 if (!mci->debugfs) in xgene_edac_mc_create_debugfs_node()
170 edac_debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci, in xgene_edac_mc_create_debugfs_node()
176 struct xgene_edac_mc_ctx *ctx = mci->pvt_info; in xgene_edac_mc_check()
185 xgene_edac_pcp_rd(ctx->edac, PCPHPERRINTSTS, &pcp_hp_stat); in xgene_edac_mc_check()
186 xgene_edac_pcp_rd(ctx->edac, PCPLPERRINTSTS, &pcp_lp_stat); in xgene_edac_mc_check()
193 reg = readl(ctx->mcu_csr + MCUESRR0 + rank * MCU_RANK_STRIDE); in xgene_edac_mc_check()
199 edac_mc_chipset_printk(mci, KERN_ERR, "X-Gene", in xgene_edac_mc_check()
203 1, 0, 0, 0, 0, 0, -1, mci->ctl_name, ""); in xgene_edac_mc_check()
208 bank = readl(ctx->mcu_csr + MCUEBLRR0 + in xgene_edac_mc_check()
210 col_row = readl(ctx->mcu_csr + MCUERCRR0 + in xgene_edac_mc_check()
212 count = readl(ctx->mcu_csr + MCUSBECNT0 + in xgene_edac_mc_check()
214 edac_mc_chipset_printk(mci, KERN_WARNING, "X-Gene", in xgene_edac_mc_check()
222 1, 0, 0, 0, 0, 0, -1, mci->ctl_name, ""); in xgene_edac_mc_check()
226 writel(0x0, ctx->mcu_csr + MCUEBLRR0 + rank * MCU_RANK_STRIDE); in xgene_edac_mc_check()
227 writel(0x0, ctx->mcu_csr + MCUERCRR0 + rank * MCU_RANK_STRIDE); in xgene_edac_mc_check()
228 writel(0x0, ctx->mcu_csr + MCUSBECNT0 + in xgene_edac_mc_check()
230 writel(reg, ctx->mcu_csr + MCUESRR0 + rank * MCU_RANK_STRIDE); in xgene_edac_mc_check()
234 reg = readl(ctx->mcu_csr + MCUGESR); in xgene_edac_mc_check()
237 edac_mc_chipset_printk(mci, KERN_WARNING, "X-Gene", in xgene_edac_mc_check()
238 "MCU address miss-match error\n"); in xgene_edac_mc_check()
240 edac_mc_chipset_printk(mci, KERN_WARNING, "X-Gene", in xgene_edac_mc_check()
241 "MCU address multi-match error\n"); in xgene_edac_mc_check()
243 writel(reg, ctx->mcu_csr + MCUGESR); in xgene_edac_mc_check()
249 struct xgene_edac_mc_ctx *ctx = mci->pvt_info; in xgene_edac_mc_irq_ctl()
255 mutex_lock(&ctx->edac->mc_lock); in xgene_edac_mc_irq_ctl()
258 * As there is only single bit for enable error and interrupt mask, in xgene_edac_mc_irq_ctl()
259 * we must only enable top level interrupt after all MCUs are in xgene_edac_mc_irq_ctl()
261 * MCU has not registered, the interrupt will never get cleared. To in xgene_edac_mc_irq_ctl()
267 ctx->edac->mc_registered_mask |= 1 << ctx->mcu_id; in xgene_edac_mc_irq_ctl()
269 /* Enable interrupt after all active MCU registered */ in xgene_edac_mc_irq_ctl()
270 if (ctx->edac->mc_registered_mask == in xgene_edac_mc_irq_ctl()
271 ctx->edac->mc_active_mask) { in xgene_edac_mc_irq_ctl()
272 /* Enable memory controller top level interrupt */ in xgene_edac_mc_irq_ctl()
273 xgene_edac_pcp_clrbits(ctx->edac, PCPHPERRINTMSK, in xgene_edac_mc_irq_ctl()
276 xgene_edac_pcp_clrbits(ctx->edac, PCPLPERRINTMSK, in xgene_edac_mc_irq_ctl()
280 /* Enable MCU interrupt and error reporting */ in xgene_edac_mc_irq_ctl()
281 val = readl(ctx->mcu_csr + MCUGECR); in xgene_edac_mc_irq_ctl()
286 writel(val, ctx->mcu_csr + MCUGECR); in xgene_edac_mc_irq_ctl()
288 /* Disable MCU interrupt */ in xgene_edac_mc_irq_ctl()
289 val = readl(ctx->mcu_csr + MCUGECR); in xgene_edac_mc_irq_ctl()
294 writel(val, ctx->mcu_csr + MCUGECR); in xgene_edac_mc_irq_ctl()
296 /* Disable memory controller top level interrupt */ in xgene_edac_mc_irq_ctl()
297 xgene_edac_pcp_setbits(ctx->edac, PCPHPERRINTMSK, in xgene_edac_mc_irq_ctl()
299 xgene_edac_pcp_setbits(ctx->edac, PCPLPERRINTMSK, in xgene_edac_mc_irq_ctl()
303 ctx->edac->mc_registered_mask &= ~(1 << ctx->mcu_id); in xgene_edac_mc_irq_ctl()
306 mutex_unlock(&ctx->edac->mc_lock); in xgene_edac_mc_irq_ctl()
314 if (regmap_read(ctx->edac->csw_map, CSW_CSWCR, ®)) in xgene_edac_mc_is_active()
319 * Dual MCB active - Determine if all 4 active or just MCU0 in xgene_edac_mc_is_active()
322 if (regmap_read(ctx->edac->mcbb_map, MCBADDRMR, ®)) in xgene_edac_mc_is_active()
327 * Single MCB active - Determine if MCU0/MCU1 or just MCU0 in xgene_edac_mc_is_active()
330 if (regmap_read(ctx->edac->mcba_map, MCBADDRMR, ®)) in xgene_edac_mc_is_active()
336 if (!ctx->edac->mc_active_mask) in xgene_edac_mc_is_active()
337 ctx->edac->mc_active_mask = mcu_mask; in xgene_edac_mc_is_active()
354 if (!devres_open_group(edac->dev, xgene_edac_mc_add, GFP_KERNEL)) in xgene_edac_mc_add()
355 return -ENOMEM; in xgene_edac_mc_add()
359 dev_err(edac->dev, "no MCU resource address\n"); in xgene_edac_mc_add()
362 tmp_ctx.mcu_csr = devm_ioremap_resource(edac->dev, &res); in xgene_edac_mc_add()
364 dev_err(edac->dev, "unable to map MCU resource\n"); in xgene_edac_mc_add()
369 /* Ignore non-active MCU */ in xgene_edac_mc_add()
370 if (of_property_read_u32(np, "memory-controller", &tmp_ctx.mcu_id)) { in xgene_edac_mc_add()
371 dev_err(edac->dev, "no memory-controller property\n"); in xgene_edac_mc_add()
372 rc = -ENODEV; in xgene_edac_mc_add()
376 rc = -ENODEV; in xgene_edac_mc_add()
389 rc = -ENOMEM; in xgene_edac_mc_add()
393 ctx = mci->pvt_info; in xgene_edac_mc_add()
395 ctx->name = "xgene_edac_mc_err"; in xgene_edac_mc_add()
396 ctx->mci = mci; in xgene_edac_mc_add()
397 mci->pdev = &mci->dev; in xgene_edac_mc_add()
398 mci->ctl_name = ctx->name; in xgene_edac_mc_add()
399 mci->dev_name = ctx->name; in xgene_edac_mc_add()
401 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 | MEM_FLAG_RDDR3 | in xgene_edac_mc_add()
403 mci->edac_ctl_cap = EDAC_FLAG_SECDED; in xgene_edac_mc_add()
404 mci->edac_cap = EDAC_FLAG_SECDED; in xgene_edac_mc_add()
405 mci->mod_name = EDAC_MOD_STR; in xgene_edac_mc_add()
406 mci->ctl_page_to_phys = NULL; in xgene_edac_mc_add()
407 mci->scrub_cap = SCRUB_FLAG_HW_SRC; in xgene_edac_mc_add()
408 mci->scrub_mode = SCRUB_HW_SRC; in xgene_edac_mc_add()
411 mci->edac_check = xgene_edac_mc_check; in xgene_edac_mc_add()
414 dev_err(edac->dev, "edac_mc_add_mc failed\n"); in xgene_edac_mc_add()
415 rc = -EINVAL; in xgene_edac_mc_add()
421 list_add(&ctx->next, &edac->mcus); in xgene_edac_mc_add()
425 devres_remove_group(edac->dev, xgene_edac_mc_add); in xgene_edac_mc_add()
427 dev_info(edac->dev, "X-Gene EDAC MC registered\n"); in xgene_edac_mc_add()
433 devres_release_group(edac->dev, xgene_edac_mc_add); in xgene_edac_mc_add()
439 xgene_edac_mc_irq_ctl(mcu->mci, false); in xgene_edac_mc_remove()
440 edac_mc_del_mc(&mcu->mci->dev); in xgene_edac_mc_remove()
441 edac_mc_free(mcu->mci); in xgene_edac_mc_remove()
454 #define MEMERR_CPU_ICFESR_ERRWAY_RD(src) (((src) & 0xFF000000) >> 24) argument
455 #define MEMERR_CPU_ICFESR_ERRINDEX_RD(src) (((src) & 0x003F0000) >> 16) argument
456 #define MEMERR_CPU_ICFESR_ERRINFO_RD(src) (((src) & 0x0000FF00) >> 8) argument
457 #define MEMERR_CPU_ICFESR_ERRTYPE_RD(src) (((src) & 0x00000070) >> 4) argument
461 #define MEMERR_CPU_LSUESR_ERRWAY_RD(src) (((src) & 0xFF000000) >> 24) argument
462 #define MEMERR_CPU_LSUESR_ERRINDEX_RD(src) (((src) & 0x003F0000) >> 16) argument
463 #define MEMERR_CPU_LSUESR_ERRINFO_RD(src) (((src) & 0x0000FF00) >> 8) argument
464 #define MEMERR_CPU_LSUESR_ERRTYPE_RD(src) (((src) & 0x00000070) >> 4) argument
470 #define MEMERR_CPU_MMUESR_ERRWAY_RD(src) (((src) & 0xFF000000) >> 24) argument
471 #define MEMERR_CPU_MMUESR_ERRINDEX_RD(src) (((src) & 0x007F0000) >> 16) argument
472 #define MEMERR_CPU_MMUESR_ERRINFO_RD(src) (((src) & 0x0000FF00) >> 8) argument
474 #define MEMERR_CPU_MMUESR_ERRTYPE_RD(src) (((src) & 0x00000070) >> 4) argument
483 #define MEMERR_L2C_L2ESR_ERRSYN_RD(src) (((src) & 0xFF000000) >> 24) argument
484 #define MEMERR_L2C_L2ESR_ERRWAY_RD(src) (((src) & 0x00FC0000) >> 18) argument
485 #define MEMERR_L2C_L2ESR_ERRCPU_RD(src) (((src) & 0x00020000) >> 17) argument
486 #define MEMERR_L2C_L2ESR_ERRGROUP_RD(src) (((src) & 0x0000E000) >> 13) argument
487 #define MEMERR_L2C_L2ESR_ERRACTION_RD(src) (((src) & 0x00001C00) >> 10) argument
488 #define MEMERR_L2C_L2ESR_ERRTYPE_RD(src) (((src) & 0x00000300) >> 8) argument
504 * Processor Module Domain (PMD) context - Context for a pair of processors.
522 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; in xgene_edac_pmd_l1_check()
526 pg_f = ctx->pmd_csr + cpu_idx * CPU_CSR_STRIDE + CPU_MEMERR_CPU_PAGE; in xgene_edac_pmd_l1_check()
531 dev_err(edac_dev->dev, in xgene_edac_pmd_l1_check()
533 ctx->pmd * MAX_CPU_PER_PMD + cpu_idx, val, in xgene_edac_pmd_l1_check()
538 dev_err(edac_dev->dev, "One or more correctable error\n"); in xgene_edac_pmd_l1_check()
540 dev_err(edac_dev->dev, "Multiple correctable error\n"); in xgene_edac_pmd_l1_check()
543 dev_err(edac_dev->dev, "L1 TLB multiple hit\n"); in xgene_edac_pmd_l1_check()
546 dev_err(edac_dev->dev, "Way select multiple hit\n"); in xgene_edac_pmd_l1_check()
549 dev_err(edac_dev->dev, "Physical tag parity error\n"); in xgene_edac_pmd_l1_check()
553 dev_err(edac_dev->dev, "L1 data parity error\n"); in xgene_edac_pmd_l1_check()
556 dev_err(edac_dev->dev, "L1 pre-decode parity error\n"); in xgene_edac_pmd_l1_check()
565 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); in xgene_edac_pmd_l1_check()
571 dev_err(edac_dev->dev, in xgene_edac_pmd_l1_check()
573 ctx->pmd * MAX_CPU_PER_PMD + cpu_idx, val, in xgene_edac_pmd_l1_check()
578 dev_err(edac_dev->dev, "One or more correctable error\n"); in xgene_edac_pmd_l1_check()
580 dev_err(edac_dev->dev, "Multiple correctable error\n"); in xgene_edac_pmd_l1_check()
583 dev_err(edac_dev->dev, "Load tag error\n"); in xgene_edac_pmd_l1_check()
586 dev_err(edac_dev->dev, "Load data error\n"); in xgene_edac_pmd_l1_check()
589 dev_err(edac_dev->dev, "WSL multihit error\n"); in xgene_edac_pmd_l1_check()
592 dev_err(edac_dev->dev, "Store tag error\n"); in xgene_edac_pmd_l1_check()
595 dev_err(edac_dev->dev, in xgene_edac_pmd_l1_check()
599 dev_err(edac_dev->dev, in xgene_edac_pmd_l1_check()
609 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); in xgene_edac_pmd_l1_check()
615 dev_err(edac_dev->dev, in xgene_edac_pmd_l1_check()
617 ctx->pmd * MAX_CPU_PER_PMD + cpu_idx, val, in xgene_edac_pmd_l1_check()
623 dev_err(edac_dev->dev, "One or more correctable error\n"); in xgene_edac_pmd_l1_check()
625 dev_err(edac_dev->dev, "Multiple correctable error\n"); in xgene_edac_pmd_l1_check()
628 dev_err(edac_dev->dev, "Stage 1 UTB hit error\n"); in xgene_edac_pmd_l1_check()
631 dev_err(edac_dev->dev, "Stage 1 UTB miss error\n"); in xgene_edac_pmd_l1_check()
634 dev_err(edac_dev->dev, "Stage 1 UTB allocate error\n"); in xgene_edac_pmd_l1_check()
637 dev_err(edac_dev->dev, "TMO operation single bank error\n"); in xgene_edac_pmd_l1_check()
640 dev_err(edac_dev->dev, "Stage 2 UTB error\n"); in xgene_edac_pmd_l1_check()
643 dev_err(edac_dev->dev, "Stage 2 UTB miss error\n"); in xgene_edac_pmd_l1_check()
646 dev_err(edac_dev->dev, "Stage 2 UTB allocate error\n"); in xgene_edac_pmd_l1_check()
649 dev_err(edac_dev->dev, "TMO operation multiple bank error\n"); in xgene_edac_pmd_l1_check()
656 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); in xgene_edac_pmd_l1_check()
661 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; in xgene_edac_pmd_l2_check()
669 pg_e = ctx->pmd_csr + CPU_MEMERR_L2C_PAGE; in xgene_edac_pmd_l2_check()
675 dev_err(edac_dev->dev, in xgene_edac_pmd_l2_check()
677 ctx->pmd, val, val_hi, val_lo); in xgene_edac_pmd_l2_check()
678 dev_err(edac_dev->dev, in xgene_edac_pmd_l2_check()
687 dev_err(edac_dev->dev, "One or more correctable error\n"); in xgene_edac_pmd_l2_check()
689 dev_err(edac_dev->dev, "Multiple correctable error\n"); in xgene_edac_pmd_l2_check()
691 dev_err(edac_dev->dev, "One or more uncorrectable error\n"); in xgene_edac_pmd_l2_check()
693 dev_err(edac_dev->dev, "Multiple uncorrectable error\n"); in xgene_edac_pmd_l2_check()
697 dev_err(edac_dev->dev, "Outbound SDB parity error\n"); in xgene_edac_pmd_l2_check()
700 dev_err(edac_dev->dev, "Inbound SDB parity error\n"); in xgene_edac_pmd_l2_check()
703 dev_err(edac_dev->dev, "Tag ECC error\n"); in xgene_edac_pmd_l2_check()
706 dev_err(edac_dev->dev, "Data ECC error\n"); in xgene_edac_pmd_l2_check()
715 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); in xgene_edac_pmd_l2_check()
718 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); in xgene_edac_pmd_l2_check()
722 pg_d = ctx->pmd_csr + CPU_L2C_PAGE; in xgene_edac_pmd_l2_check()
727 dev_err(edac_dev->dev, in xgene_edac_pmd_l2_check()
729 ctx->pmd, val, val_hi, val_lo); in xgene_edac_pmd_l2_check()
736 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; in xgene_edac_pmd_check()
740 xgene_edac_pcp_rd(ctx->edac, PCPHPERRINTSTS, &pcp_hp_stat); in xgene_edac_pmd_check()
741 if (!((PMD0_MERR_MASK << ctx->pmd) & pcp_hp_stat)) in xgene_edac_pmd_check()
755 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; in xgene_edac_pmd_cpu_hw_cfg()
756 void __iomem *pg_f = ctx->pmd_csr + cpu * CPU_CSR_STRIDE + in xgene_edac_pmd_cpu_hw_cfg()
770 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; in xgene_edac_pmd_hw_cfg()
771 void __iomem *pg_d = ctx->pmd_csr + CPU_L2C_PAGE; in xgene_edac_pmd_hw_cfg()
772 void __iomem *pg_e = ctx->pmd_csr + CPU_MEMERR_L2C_PAGE; in xgene_edac_pmd_hw_cfg()
774 /* Enable PMD memory error - MEMERR_L2C_L2ECR and L2C_L2RTOCR */ in xgene_edac_pmd_hw_cfg()
777 if (ctx->version > 1) in xgene_edac_pmd_hw_cfg()
784 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; in xgene_edac_pmd_hw_ctl()
787 /* Enable PMD error interrupt */ in xgene_edac_pmd_hw_ctl()
788 if (edac_dev->op_state == OP_RUNNING_INTERRUPT) { in xgene_edac_pmd_hw_ctl()
790 xgene_edac_pcp_clrbits(ctx->edac, PCPHPERRINTMSK, in xgene_edac_pmd_hw_ctl()
791 PMD0_MERR_MASK << ctx->pmd); in xgene_edac_pmd_hw_ctl()
793 xgene_edac_pcp_setbits(ctx->edac, PCPHPERRINTMSK, in xgene_edac_pmd_hw_ctl()
794 PMD0_MERR_MASK << ctx->pmd); in xgene_edac_pmd_hw_ctl()
810 struct edac_device_ctl_info *edac_dev = file->private_data; in xgene_edac_pmd_l1_inject_ctrl_write()
811 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; in xgene_edac_pmd_l1_inject_ctrl_write()
816 cpux_pg_f = ctx->pmd_csr + i * CPU_CSR_STRIDE + in xgene_edac_pmd_l1_inject_ctrl_write()
836 struct edac_device_ctl_info *edac_dev = file->private_data; in xgene_edac_pmd_l2_inject_ctrl_write()
837 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; in xgene_edac_pmd_l2_inject_ctrl_write()
838 void __iomem *pg_e = ctx->pmd_csr + CPU_MEMERR_L2C_PAGE; in xgene_edac_pmd_l2_inject_ctrl_write()
863 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info; in xgene_edac_pmd_create_debugfs_nodes()
867 if (!IS_ENABLED(CONFIG_EDAC_DEBUG) || !ctx->edac->dfs) in xgene_edac_pmd_create_debugfs_nodes()
870 snprintf(name, sizeof(name), "PMD%d", ctx->pmd); in xgene_edac_pmd_create_debugfs_nodes()
871 dbgfs_dir = edac_debugfs_create_dir_at(name, ctx->edac->dfs); in xgene_edac_pmd_create_debugfs_nodes()
897 if (!devres_open_group(edac->dev, xgene_edac_pmd_add, GFP_KERNEL)) in xgene_edac_pmd_add()
898 return -ENOMEM; in xgene_edac_pmd_add()
901 if (of_property_read_u32(np, "pmd-controller", &pmd)) { in xgene_edac_pmd_add()
902 dev_err(edac->dev, "no pmd-controller property\n"); in xgene_edac_pmd_add()
903 rc = -ENODEV; in xgene_edac_pmd_add()
906 rc = regmap_read(edac->efuse_map, 0, &val); in xgene_edac_pmd_add()
910 rc = -ENODEV; in xgene_edac_pmd_add()
919 rc = -ENOMEM; in xgene_edac_pmd_add()
923 ctx = edac_dev->pvt_info; in xgene_edac_pmd_add()
924 ctx->name = "xgene_pmd_err"; in xgene_edac_pmd_add()
925 ctx->pmd = pmd; in xgene_edac_pmd_add()
926 ctx->edac = edac; in xgene_edac_pmd_add()
927 ctx->edac_dev = edac_dev; in xgene_edac_pmd_add()
928 ctx->ddev = *edac->dev; in xgene_edac_pmd_add()
929 ctx->version = version; in xgene_edac_pmd_add()
930 edac_dev->dev = &ctx->ddev; in xgene_edac_pmd_add()
931 edac_dev->ctl_name = ctx->name; in xgene_edac_pmd_add()
932 edac_dev->dev_name = ctx->name; in xgene_edac_pmd_add()
933 edac_dev->mod_name = EDAC_MOD_STR; in xgene_edac_pmd_add()
937 dev_err(edac->dev, "no PMD resource address\n"); in xgene_edac_pmd_add()
940 ctx->pmd_csr = devm_ioremap_resource(edac->dev, &res); in xgene_edac_pmd_add()
941 if (IS_ERR(ctx->pmd_csr)) { in xgene_edac_pmd_add()
942 dev_err(edac->dev, in xgene_edac_pmd_add()
944 rc = PTR_ERR(ctx->pmd_csr); in xgene_edac_pmd_add()
949 edac_dev->edac_check = xgene_edac_pmd_check; in xgene_edac_pmd_add()
955 dev_err(edac->dev, "edac_device_add_device failed\n"); in xgene_edac_pmd_add()
956 rc = -ENOMEM; in xgene_edac_pmd_add()
961 edac_dev->op_state = OP_RUNNING_INTERRUPT; in xgene_edac_pmd_add()
963 list_add(&ctx->next, &edac->pmds); in xgene_edac_pmd_add()
967 devres_remove_group(edac->dev, xgene_edac_pmd_add); in xgene_edac_pmd_add()
969 dev_info(edac->dev, "X-Gene EDAC PMD%d registered\n", ctx->pmd); in xgene_edac_pmd_add()
975 devres_release_group(edac->dev, xgene_edac_pmd_add); in xgene_edac_pmd_add()
981 struct edac_device_ctl_info *edac_dev = pmd->edac_dev; in xgene_edac_pmd_remove()
984 edac_device_del_device(edac_dev->dev); in xgene_edac_pmd_remove()
1006 #define L3C_ELR_ERRSYN(src) ((src & 0xFF800000) >> 23) argument
1007 #define L3C_ELR_ERRWAY(src) ((src & 0x007E0000) >> 17) argument
1008 #define L3C_ELR_AGENTID(src) ((src & 0x0001E000) >> 13) argument
1009 #define L3C_ELR_ERRGRP(src) ((src & 0x00000F00) >> 8) argument
1010 #define L3C_ELR_OPTYPE(src) ((src & 0x000000F0) >> 4) argument
1011 #define L3C_ELR_PADDRHIGH(src) (src & 0x0000000F) argument
1014 #define L3C_BELR_BANK(src) (src & 0x0000000F) argument
1055 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; in xgene_edac_l3_check()
1061 l3cesr = readl(ctx->dev_csr + L3C_ESR); in xgene_edac_l3_check()
1066 dev_err(edac_dev->dev, "L3C uncorrectable error\n"); in xgene_edac_l3_check()
1068 dev_warn(edac_dev->dev, "L3C correctable error\n"); in xgene_edac_l3_check()
1070 l3celr = readl(ctx->dev_csr + L3C_ELR); in xgene_edac_l3_check()
1071 l3caelr = readl(ctx->dev_csr + L3C_AELR); in xgene_edac_l3_check()
1072 l3cbelr = readl(ctx->dev_csr + L3C_BELR); in xgene_edac_l3_check()
1074 dev_err(edac_dev->dev, "L3C multiple hit error\n"); in xgene_edac_l3_check()
1076 dev_err(edac_dev->dev, in xgene_edac_l3_check()
1079 dev_err(edac_dev->dev, "L3C multiple uncorrectable error\n"); in xgene_edac_l3_check()
1081 dev_err(edac_dev->dev, in xgene_edac_l3_check()
1085 dev_err(edac_dev->dev, in xgene_edac_l3_check()
1093 dev_err(edac_dev->dev, "L3C error address 0x%08X.%08X bank %d\n", in xgene_edac_l3_check()
1096 dev_err(edac_dev->dev, in xgene_edac_l3_check()
1099 /* Clear L3C error interrupt */ in xgene_edac_l3_check()
1100 writel(0, ctx->dev_csr + L3C_ESR); in xgene_edac_l3_check()
1102 if (ctx->version <= 1 && in xgene_edac_l3_check()
1104 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); in xgene_edac_l3_check()
1108 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); in xgene_edac_l3_check()
1110 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); in xgene_edac_l3_check()
1116 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; in xgene_edac_l3_hw_init()
1119 val = readl(ctx->dev_csr + L3C_ECR); in xgene_edac_l3_hw_init()
1121 /* On disable, we just disable interrupt but keep error enabled */ in xgene_edac_l3_hw_init()
1122 if (edac_dev->op_state == OP_RUNNING_INTERRUPT) { in xgene_edac_l3_hw_init()
1128 writel(val, ctx->dev_csr + L3C_ECR); in xgene_edac_l3_hw_init()
1130 if (edac_dev->op_state == OP_RUNNING_INTERRUPT) { in xgene_edac_l3_hw_init()
1131 /* Enable/disable L3 error top level interrupt */ in xgene_edac_l3_hw_init()
1133 xgene_edac_pcp_clrbits(ctx->edac, PCPHPERRINTMSK, in xgene_edac_l3_hw_init()
1135 xgene_edac_pcp_clrbits(ctx->edac, PCPLPERRINTMSK, in xgene_edac_l3_hw_init()
1138 xgene_edac_pcp_setbits(ctx->edac, PCPHPERRINTMSK, in xgene_edac_l3_hw_init()
1140 xgene_edac_pcp_setbits(ctx->edac, PCPLPERRINTMSK, in xgene_edac_l3_hw_init()
1150 struct edac_device_ctl_info *edac_dev = file->private_data; in xgene_edac_l3_inject_ctrl_write()
1151 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; in xgene_edac_l3_inject_ctrl_write()
1154 writel(0xFFFFFFFF, ctx->dev_csr + L3C_ESR); in xgene_edac_l3_inject_ctrl_write()
1167 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; in xgene_edac_l3_create_debugfs_nodes()
1171 if (!IS_ENABLED(CONFIG_EDAC_DEBUG) || !ctx->edac->dfs) in xgene_edac_l3_create_debugfs_nodes()
1174 snprintf(name, sizeof(name), "l3c%d", ctx->edac_idx); in xgene_edac_l3_create_debugfs_nodes()
1175 dbgfs_dir = edac_debugfs_create_dir_at(name, ctx->edac->dfs); in xgene_edac_l3_create_debugfs_nodes()
1193 if (!devres_open_group(edac->dev, xgene_edac_l3_add, GFP_KERNEL)) in xgene_edac_l3_add()
1194 return -ENOMEM; in xgene_edac_l3_add()
1198 dev_err(edac->dev, "no L3 resource address\n"); in xgene_edac_l3_add()
1201 dev_csr = devm_ioremap_resource(edac->dev, &res); in xgene_edac_l3_add()
1203 dev_err(edac->dev, in xgene_edac_l3_add()
1213 rc = -ENOMEM; in xgene_edac_l3_add()
1217 ctx = edac_dev->pvt_info; in xgene_edac_l3_add()
1218 ctx->dev_csr = dev_csr; in xgene_edac_l3_add()
1219 ctx->name = "xgene_l3_err"; in xgene_edac_l3_add()
1220 ctx->edac_idx = edac_idx; in xgene_edac_l3_add()
1221 ctx->edac = edac; in xgene_edac_l3_add()
1222 ctx->edac_dev = edac_dev; in xgene_edac_l3_add()
1223 ctx->ddev = *edac->dev; in xgene_edac_l3_add()
1224 ctx->version = version; in xgene_edac_l3_add()
1225 edac_dev->dev = &ctx->ddev; in xgene_edac_l3_add()
1226 edac_dev->ctl_name = ctx->name; in xgene_edac_l3_add()
1227 edac_dev->dev_name = ctx->name; in xgene_edac_l3_add()
1228 edac_dev->mod_name = EDAC_MOD_STR; in xgene_edac_l3_add()
1231 edac_dev->edac_check = xgene_edac_l3_check; in xgene_edac_l3_add()
1237 dev_err(edac->dev, "failed edac_device_add_device()\n"); in xgene_edac_l3_add()
1238 rc = -ENOMEM; in xgene_edac_l3_add()
1243 edac_dev->op_state = OP_RUNNING_INTERRUPT; in xgene_edac_l3_add()
1245 list_add(&ctx->next, &edac->l3s); in xgene_edac_l3_add()
1249 devres_remove_group(edac->dev, xgene_edac_l3_add); in xgene_edac_l3_add()
1251 dev_info(edac->dev, "X-Gene EDAC L3 registered\n"); in xgene_edac_l3_add()
1257 devres_release_group(edac->dev, xgene_edac_l3_add); in xgene_edac_l3_add()
1263 struct edac_device_ctl_info *edac_dev = l3->edac_dev; in xgene_edac_l3_remove()
1266 edac_device_del_device(l3->edac->dev); in xgene_edac_l3_remove()
1278 #define REQTYPE_RD(src) (((src) & BIT(0))) argument
1279 #define ERRADDRH_RD(src) (((src) & 0xffc00000) >> 22) argument
1312 #define REQTYPE_F2_RD(src) ((src) & BIT(0)) argument
1313 #define ERRADDRH_F2_RD(src) (((src) & 0xffc00000) >> 22) argument
1323 #define ERRADDR_RD(src) ((src) & 0x03ffffff) argument
1389 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; in xgene_edac_iob_gic_report()
1395 /* GIC transaction error interrupt */ in xgene_edac_iob_gic_report()
1396 reg = readl(ctx->dev_csr + XGICTRANSERRINTSTS); in xgene_edac_iob_gic_report()
1399 dev_err(edac_dev->dev, "XGIC transaction error\n"); in xgene_edac_iob_gic_report()
1401 dev_err(edac_dev->dev, "XGIC read size error\n"); in xgene_edac_iob_gic_report()
1403 dev_err(edac_dev->dev, "Multiple XGIC read size error\n"); in xgene_edac_iob_gic_report()
1405 dev_err(edac_dev->dev, "XGIC write size error\n"); in xgene_edac_iob_gic_report()
1407 dev_err(edac_dev->dev, "Multiple XGIC write size error\n"); in xgene_edac_iob_gic_report()
1408 info = readl(ctx->dev_csr + XGICTRANSERRREQINFO); in xgene_edac_iob_gic_report()
1409 dev_err(edac_dev->dev, "XGIC %s access @ 0x%08X (0x%08X)\n", in xgene_edac_iob_gic_report()
1412 writel(reg, ctx->dev_csr + XGICTRANSERRINTSTS); in xgene_edac_iob_gic_report()
1416 reg = readl(ctx->dev_csr + GLBL_ERR_STS); in xgene_edac_iob_gic_report()
1420 err_addr_lo = readl(ctx->dev_csr + GLBL_SEC_ERRL); in xgene_edac_iob_gic_report()
1421 err_addr_hi = readl(ctx->dev_csr + GLBL_SEC_ERRH); in xgene_edac_iob_gic_report()
1422 dev_err(edac_dev->dev, in xgene_edac_iob_gic_report()
1423 "IOB single-bit correctable memory at 0x%08X.%08X error\n", in xgene_edac_iob_gic_report()
1425 writel(err_addr_lo, ctx->dev_csr + GLBL_SEC_ERRL); in xgene_edac_iob_gic_report()
1426 writel(err_addr_hi, ctx->dev_csr + GLBL_SEC_ERRH); in xgene_edac_iob_gic_report()
1429 err_addr_lo = readl(ctx->dev_csr + GLBL_MSEC_ERRL); in xgene_edac_iob_gic_report()
1430 err_addr_hi = readl(ctx->dev_csr + GLBL_MSEC_ERRH); in xgene_edac_iob_gic_report()
1431 dev_err(edac_dev->dev, in xgene_edac_iob_gic_report()
1432 "IOB multiple single-bit correctable memory at 0x%08X.%08X error\n", in xgene_edac_iob_gic_report()
1434 writel(err_addr_lo, ctx->dev_csr + GLBL_MSEC_ERRL); in xgene_edac_iob_gic_report()
1435 writel(err_addr_hi, ctx->dev_csr + GLBL_MSEC_ERRH); in xgene_edac_iob_gic_report()
1438 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); in xgene_edac_iob_gic_report()
1441 err_addr_lo = readl(ctx->dev_csr + GLBL_DED_ERRL); in xgene_edac_iob_gic_report()
1442 err_addr_hi = readl(ctx->dev_csr + GLBL_DED_ERRH); in xgene_edac_iob_gic_report()
1443 dev_err(edac_dev->dev, in xgene_edac_iob_gic_report()
1444 "IOB double-bit uncorrectable memory at 0x%08X.%08X error\n", in xgene_edac_iob_gic_report()
1446 writel(err_addr_lo, ctx->dev_csr + GLBL_DED_ERRL); in xgene_edac_iob_gic_report()
1447 writel(err_addr_hi, ctx->dev_csr + GLBL_DED_ERRH); in xgene_edac_iob_gic_report()
1450 err_addr_lo = readl(ctx->dev_csr + GLBL_MDED_ERRL); in xgene_edac_iob_gic_report()
1451 err_addr_hi = readl(ctx->dev_csr + GLBL_MDED_ERRH); in xgene_edac_iob_gic_report()
1452 dev_err(edac_dev->dev, in xgene_edac_iob_gic_report()
1453 "Multiple IOB double-bit uncorrectable memory at 0x%08X.%08X error\n", in xgene_edac_iob_gic_report()
1455 writel(err_addr_lo, ctx->dev_csr + GLBL_MDED_ERRL); in xgene_edac_iob_gic_report()
1456 writel(err_addr_hi, ctx->dev_csr + GLBL_MDED_ERRH); in xgene_edac_iob_gic_report()
1459 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); in xgene_edac_iob_gic_report()
1464 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; in xgene_edac_rb_report()
1470 if (!ctx->edac->rb_map) in xgene_edac_rb_report()
1476 * 2. Un-implemented page in xgene_edac_rb_report()
1477 * 3. Un-aligned access in xgene_edac_rb_report()
1480 if (regmap_read(ctx->edac->rb_map, RBCSR, ®)) in xgene_edac_rb_report()
1485 dev_err(edac_dev->dev, "IOB bus access error(s)\n"); in xgene_edac_rb_report()
1486 if (regmap_read(ctx->edac->rb_map, RBEIR, ®)) in xgene_edac_rb_report()
1490 dev_err(edac_dev->dev, in xgene_edac_rb_report()
1494 dev_err(edac_dev->dev, in xgene_edac_rb_report()
1498 dev_err(edac_dev->dev, in xgene_edac_rb_report()
1502 dev_err(edac_dev->dev, in xgene_edac_rb_report()
1505 if (regmap_write(ctx->edac->rb_map, RBEIR, 0)) in xgene_edac_rb_report()
1507 if (regmap_write(ctx->edac->rb_map, RBCSR, 0)) in xgene_edac_rb_report()
1512 /* IOB Bridge agent transaction error interrupt */ in xgene_edac_rb_report()
1513 reg = readl(ctx->dev_csr + IOBBATRANSERRINTSTS); in xgene_edac_rb_report()
1517 dev_err(edac_dev->dev, "IOB bridge agent (BA) transaction error\n"); in xgene_edac_rb_report()
1519 dev_err(edac_dev->dev, "IOB BA write response error\n"); in xgene_edac_rb_report()
1521 dev_err(edac_dev->dev, in xgene_edac_rb_report()
1524 dev_err(edac_dev->dev, "IOB BA XGIC poisoned write error\n"); in xgene_edac_rb_report()
1526 dev_err(edac_dev->dev, in xgene_edac_rb_report()
1529 dev_err(edac_dev->dev, "IOB BA RBM poisoned write error\n"); in xgene_edac_rb_report()
1531 dev_err(edac_dev->dev, in xgene_edac_rb_report()
1534 dev_err(edac_dev->dev, "IOB BA write error\n"); in xgene_edac_rb_report()
1536 dev_err(edac_dev->dev, "Multiple IOB BA write error\n"); in xgene_edac_rb_report()
1538 dev_err(edac_dev->dev, "IOB BA transaction error\n"); in xgene_edac_rb_report()
1540 dev_err(edac_dev->dev, "Multiple IOB BA transaction error\n"); in xgene_edac_rb_report()
1542 dev_err(edac_dev->dev, in xgene_edac_rb_report()
1545 dev_err(edac_dev->dev, in xgene_edac_rb_report()
1548 dev_err(edac_dev->dev, in xgene_edac_rb_report()
1551 dev_err(edac_dev->dev, in xgene_edac_rb_report()
1554 dev_err(edac_dev->dev, in xgene_edac_rb_report()
1557 dev_err(edac_dev->dev, in xgene_edac_rb_report()
1560 err_addr_lo = readl(ctx->dev_csr + IOBBATRANSERRREQINFOL); in xgene_edac_rb_report()
1561 err_addr_hi = readl(ctx->dev_csr + IOBBATRANSERRREQINFOH); in xgene_edac_rb_report()
1562 dev_err(edac_dev->dev, "IOB BA %s access at 0x%02X.%08X (0x%08X)\n", in xgene_edac_rb_report()
1566 dev_err(edac_dev->dev, "IOB BA requestor ID 0x%08X\n", in xgene_edac_rb_report()
1567 readl(ctx->dev_csr + IOBBATRANSERRCSWREQID)); in xgene_edac_rb_report()
1568 writel(reg, ctx->dev_csr + IOBBATRANSERRINTSTS); in xgene_edac_rb_report()
1573 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; in xgene_edac_pa_report()
1578 /* IOB Processing agent transaction error interrupt */ in xgene_edac_pa_report()
1579 reg = readl(ctx->dev_csr + IOBPATRANSERRINTSTS); in xgene_edac_pa_report()
1582 dev_err(edac_dev->dev, "IOB processing agent (PA) transaction error\n"); in xgene_edac_pa_report()
1584 dev_err(edac_dev->dev, "IOB PA read data RAM error\n"); in xgene_edac_pa_report()
1586 dev_err(edac_dev->dev, in xgene_edac_pa_report()
1589 dev_err(edac_dev->dev, "IOB PA write data RAM error\n"); in xgene_edac_pa_report()
1591 dev_err(edac_dev->dev, in xgene_edac_pa_report()
1594 dev_err(edac_dev->dev, "IOB PA transaction error\n"); in xgene_edac_pa_report()
1596 dev_err(edac_dev->dev, "Multiple IOB PA transaction error\n"); in xgene_edac_pa_report()
1598 dev_err(edac_dev->dev, "IOB PA transaction ID RAM error\n"); in xgene_edac_pa_report()
1600 dev_err(edac_dev->dev, in xgene_edac_pa_report()
1602 writel(reg, ctx->dev_csr + IOBPATRANSERRINTSTS); in xgene_edac_pa_report()
1606 reg = readl(ctx->dev_csr + IOBAXIS0TRANSERRINTSTS); in xgene_edac_pa_report()
1609 err_addr_lo = readl(ctx->dev_csr + IOBAXIS0TRANSERRREQINFOL); in xgene_edac_pa_report()
1610 err_addr_hi = readl(ctx->dev_csr + IOBAXIS0TRANSERRREQINFOH); in xgene_edac_pa_report()
1611 dev_err(edac_dev->dev, in xgene_edac_pa_report()
1616 writel(reg, ctx->dev_csr + IOBAXIS0TRANSERRINTSTS); in xgene_edac_pa_report()
1620 reg = readl(ctx->dev_csr + IOBAXIS1TRANSERRINTSTS); in xgene_edac_pa_report()
1623 err_addr_lo = readl(ctx->dev_csr + IOBAXIS1TRANSERRREQINFOL); in xgene_edac_pa_report()
1624 err_addr_hi = readl(ctx->dev_csr + IOBAXIS1TRANSERRREQINFOH); in xgene_edac_pa_report()
1625 dev_err(edac_dev->dev, in xgene_edac_pa_report()
1630 writel(reg, ctx->dev_csr + IOBAXIS1TRANSERRINTSTS); in xgene_edac_pa_report()
1635 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; in xgene_edac_soc_check()
1642 xgene_edac_pcp_rd(ctx->edac, PCPHPERRINTSTS, &pcp_hp_stat); in xgene_edac_soc_check()
1643 xgene_edac_pcp_rd(ctx->edac, PCPLPERRINTSTS, &pcp_lp_stat); in xgene_edac_soc_check()
1644 xgene_edac_pcp_rd(ctx->edac, MEMERRINTSTS, ®); in xgene_edac_soc_check()
1660 dev_info(edac_dev->dev, in xgene_edac_soc_check()
1662 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); in xgene_edac_soc_check()
1667 if (ctx->version == 1) in xgene_edac_soc_check()
1670 dev_err(edac_dev->dev, "SoC memory parity error 0x%08X\n", in xgene_edac_soc_check()
1672 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); in xgene_edac_soc_check()
1677 dev_err(edac_dev->dev, "%s memory parity error\n", in xgene_edac_soc_check()
1680 edac_dev->ctl_name); in xgene_edac_soc_check()
1688 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info; in xgene_edac_soc_hw_init()
1690 /* Enable SoC IP error interrupt */ in xgene_edac_soc_hw_init()
1691 if (edac_dev->op_state == OP_RUNNING_INTERRUPT) { in xgene_edac_soc_hw_init()
1693 xgene_edac_pcp_clrbits(ctx->edac, PCPHPERRINTMSK, in xgene_edac_soc_hw_init()
1698 xgene_edac_pcp_clrbits(ctx->edac, PCPLPERRINTMSK, in xgene_edac_soc_hw_init()
1701 xgene_edac_pcp_setbits(ctx->edac, PCPHPERRINTMSK, in xgene_edac_soc_hw_init()
1706 xgene_edac_pcp_setbits(ctx->edac, PCPLPERRINTMSK, in xgene_edac_soc_hw_init()
1711 ctx->dev_csr + IOBAXIS0TRANSERRINTMSK); in xgene_edac_soc_hw_init()
1713 ctx->dev_csr + IOBAXIS1TRANSERRINTMSK); in xgene_edac_soc_hw_init()
1715 ctx->dev_csr + XGICTRANSERRINTMSK); in xgene_edac_soc_hw_init()
1717 xgene_edac_pcp_setbits(ctx->edac, MEMERRINTMSK, in xgene_edac_soc_hw_init()
1732 if (!devres_open_group(edac->dev, xgene_edac_soc_add, GFP_KERNEL)) in xgene_edac_soc_add()
1733 return -ENOMEM; in xgene_edac_soc_add()
1737 dev_err(edac->dev, "no SoC resource address\n"); in xgene_edac_soc_add()
1740 dev_csr = devm_ioremap_resource(edac->dev, &res); in xgene_edac_soc_add()
1742 dev_err(edac->dev, in xgene_edac_soc_add()
1752 rc = -ENOMEM; in xgene_edac_soc_add()
1756 ctx = edac_dev->pvt_info; in xgene_edac_soc_add()
1757 ctx->dev_csr = dev_csr; in xgene_edac_soc_add()
1758 ctx->name = "xgene_soc_err"; in xgene_edac_soc_add()
1759 ctx->edac_idx = edac_idx; in xgene_edac_soc_add()
1760 ctx->edac = edac; in xgene_edac_soc_add()
1761 ctx->edac_dev = edac_dev; in xgene_edac_soc_add()
1762 ctx->ddev = *edac->dev; in xgene_edac_soc_add()
1763 ctx->version = version; in xgene_edac_soc_add()
1764 edac_dev->dev = &ctx->ddev; in xgene_edac_soc_add()
1765 edac_dev->ctl_name = ctx->name; in xgene_edac_soc_add()
1766 edac_dev->dev_name = ctx->name; in xgene_edac_soc_add()
1767 edac_dev->mod_name = EDAC_MOD_STR; in xgene_edac_soc_add()
1770 edac_dev->edac_check = xgene_edac_soc_check; in xgene_edac_soc_add()
1774 dev_err(edac->dev, "failed edac_device_add_device()\n"); in xgene_edac_soc_add()
1775 rc = -ENOMEM; in xgene_edac_soc_add()
1780 edac_dev->op_state = OP_RUNNING_INTERRUPT; in xgene_edac_soc_add()
1782 list_add(&ctx->next, &edac->socs); in xgene_edac_soc_add()
1786 devres_remove_group(edac->dev, xgene_edac_soc_add); in xgene_edac_soc_add()
1788 dev_info(edac->dev, "X-Gene EDAC SoC registered\n"); in xgene_edac_soc_add()
1795 devres_release_group(edac->dev, xgene_edac_soc_add); in xgene_edac_soc_add()
1801 struct edac_device_ctl_info *edac_dev = soc->edac_dev; in xgene_edac_soc_remove()
1804 edac_device_del_device(soc->edac->dev); in xgene_edac_soc_remove()
1824 list_for_each_entry(mcu, &ctx->mcus, next) in xgene_edac_isr()
1825 xgene_edac_mc_check(mcu->mci); in xgene_edac_isr()
1828 list_for_each_entry(pmd, &ctx->pmds, next) { in xgene_edac_isr()
1829 if ((PMD0_MERR_MASK << pmd->pmd) & pcp_hp_stat) in xgene_edac_isr()
1830 xgene_edac_pmd_check(pmd->edac_dev); in xgene_edac_isr()
1833 list_for_each_entry(node, &ctx->l3s, next) in xgene_edac_isr()
1834 xgene_edac_l3_check(node->edac_dev); in xgene_edac_isr()
1836 list_for_each_entry(node, &ctx->socs, next) in xgene_edac_isr()
1837 xgene_edac_soc_check(node->edac_dev); in xgene_edac_isr()
1849 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL); in xgene_edac_probe()
1851 return -ENOMEM; in xgene_edac_probe()
1853 edac->dev = &pdev->dev; in xgene_edac_probe()
1855 INIT_LIST_HEAD(&edac->mcus); in xgene_edac_probe()
1856 INIT_LIST_HEAD(&edac->pmds); in xgene_edac_probe()
1857 INIT_LIST_HEAD(&edac->l3s); in xgene_edac_probe()
1858 INIT_LIST_HEAD(&edac->socs); in xgene_edac_probe()
1859 spin_lock_init(&edac->lock); in xgene_edac_probe()
1860 mutex_init(&edac->mc_lock); in xgene_edac_probe()
1862 edac->csw_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in xgene_edac_probe()
1863 "regmap-csw"); in xgene_edac_probe()
1864 if (IS_ERR(edac->csw_map)) { in xgene_edac_probe()
1865 dev_err(edac->dev, "unable to get syscon regmap csw\n"); in xgene_edac_probe()
1866 rc = PTR_ERR(edac->csw_map); in xgene_edac_probe()
1870 edac->mcba_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in xgene_edac_probe()
1871 "regmap-mcba"); in xgene_edac_probe()
1872 if (IS_ERR(edac->mcba_map)) { in xgene_edac_probe()
1873 dev_err(edac->dev, "unable to get syscon regmap mcba\n"); in xgene_edac_probe()
1874 rc = PTR_ERR(edac->mcba_map); in xgene_edac_probe()
1878 edac->mcbb_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in xgene_edac_probe()
1879 "regmap-mcbb"); in xgene_edac_probe()
1880 if (IS_ERR(edac->mcbb_map)) { in xgene_edac_probe()
1881 dev_err(edac->dev, "unable to get syscon regmap mcbb\n"); in xgene_edac_probe()
1882 rc = PTR_ERR(edac->mcbb_map); in xgene_edac_probe()
1885 edac->efuse_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in xgene_edac_probe()
1886 "regmap-efuse"); in xgene_edac_probe()
1887 if (IS_ERR(edac->efuse_map)) { in xgene_edac_probe()
1888 dev_err(edac->dev, "unable to get syscon regmap efuse\n"); in xgene_edac_probe()
1889 rc = PTR_ERR(edac->efuse_map); in xgene_edac_probe()
1897 edac->rb_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in xgene_edac_probe()
1898 "regmap-rb"); in xgene_edac_probe()
1899 if (IS_ERR(edac->rb_map)) { in xgene_edac_probe()
1900 dev_warn(edac->dev, "missing syscon regmap rb\n"); in xgene_edac_probe()
1901 edac->rb_map = NULL; in xgene_edac_probe()
1905 edac->pcp_csr = devm_ioremap_resource(&pdev->dev, res); in xgene_edac_probe()
1906 if (IS_ERR(edac->pcp_csr)) { in xgene_edac_probe()
1907 dev_err(&pdev->dev, "no PCP resource address\n"); in xgene_edac_probe()
1908 rc = PTR_ERR(edac->pcp_csr); in xgene_edac_probe()
1919 dev_err(&pdev->dev, "No IRQ resource\n"); in xgene_edac_probe()
1923 rc = devm_request_irq(&pdev->dev, irq, in xgene_edac_probe()
1925 dev_name(&pdev->dev), edac); in xgene_edac_probe()
1927 dev_err(&pdev->dev, in xgene_edac_probe()
1934 edac->dfs = edac_debugfs_create_dir(pdev->dev.kobj.name); in xgene_edac_probe()
1936 for_each_child_of_node(pdev->dev.of_node, child) { in xgene_edac_probe()
1939 if (of_device_is_compatible(child, "apm,xgene-edac-mc")) in xgene_edac_probe()
1941 if (of_device_is_compatible(child, "apm,xgene-edac-pmd")) in xgene_edac_probe()
1943 if (of_device_is_compatible(child, "apm,xgene-edac-pmd-v2")) in xgene_edac_probe()
1945 if (of_device_is_compatible(child, "apm,xgene-edac-l3")) in xgene_edac_probe()
1947 if (of_device_is_compatible(child, "apm,xgene-edac-l3-v2")) in xgene_edac_probe()
1949 if (of_device_is_compatible(child, "apm,xgene-edac-soc")) in xgene_edac_probe()
1951 if (of_device_is_compatible(child, "apm,xgene-edac-soc-v1")) in xgene_edac_probe()
1963 struct xgene_edac *edac = dev_get_drvdata(&pdev->dev); in xgene_edac_remove()
1971 list_for_each_entry_safe(mcu, temp_mcu, &edac->mcus, next) in xgene_edac_remove()
1974 list_for_each_entry_safe(pmd, temp_pmd, &edac->pmds, next) in xgene_edac_remove()
1977 list_for_each_entry_safe(node, temp_node, &edac->l3s, next) in xgene_edac_remove()
1980 list_for_each_entry_safe(node, temp_node, &edac->socs, next) in xgene_edac_remove()
1985 { .compatible = "apm,xgene-edac" },
1994 .name = "xgene-edac",
2004 return -EBUSY; in xgene_edac_init()
2038 MODULE_DESCRIPTION("APM X-Gene EDAC driver");
2041 "EDAC error reporting state: 0=Poll, 2=Interrupt");