1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) ST-Ericsson SA 2007-2010
4  * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5  * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
31 	u32 l1 = 0; /* src */  in d40_log_cfg()
33 	/* src is mem? -> increase address pos */  in d40_log_cfg()
34 	if (cfg->dir ==  DMA_MEM_TO_DEV ||  in d40_log_cfg()
35 	    cfg->dir ==  DMA_MEM_TO_MEM)  in d40_log_cfg()
38 	/* dst is mem? -> increase address pos */  in d40_log_cfg()
39 	if (cfg->dir ==  DMA_DEV_TO_MEM ||  in d40_log_cfg()
40 	    cfg->dir ==  DMA_MEM_TO_MEM)  in d40_log_cfg()
43 	/* src is hw? -> master port 1 */  in d40_log_cfg()
44 	if (cfg->dir ==  DMA_DEV_TO_MEM ||  in d40_log_cfg()
45 	    cfg->dir ==  DMA_DEV_TO_DEV)  in d40_log_cfg()
48 	/* dst is hw? -> master port 1 */  in d40_log_cfg()
49 	if (cfg->dir ==  DMA_MEM_TO_DEV ||  in d40_log_cfg()
50 	    cfg->dir ==  DMA_DEV_TO_DEV)  in d40_log_cfg()
54 	l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;  in d40_log_cfg()
55 	l3 |= d40_width_to_bits(cfg->dst_info.data_width)  in d40_log_cfg()
59 	l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;  in d40_log_cfg()
60 	l1 |= d40_width_to_bits(cfg->src_info.data_width)  in d40_log_cfg()
70 	u32 src = 0;  in d40_phy_cfg()  local
73 	if ((cfg->dir == DMA_DEV_TO_MEM) ||  in d40_phy_cfg()
74 	    (cfg->dir == DMA_DEV_TO_DEV)) {  in d40_phy_cfg()
76 		src |= BIT(D40_SREG_CFG_MST_POS);  in d40_phy_cfg()
77 		src |= D40_TYPE_TO_EVENT(cfg->dev_type);  in d40_phy_cfg()
79 		if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)  in d40_phy_cfg()
80 			src |= BIT(D40_SREG_CFG_PHY_TM_POS);  in d40_phy_cfg()
82 			src |= 3 << D40_SREG_CFG_PHY_TM_POS;  in d40_phy_cfg()
84 	if ((cfg->dir == DMA_MEM_TO_DEV) ||  in d40_phy_cfg()
85 	    (cfg->dir == DMA_DEV_TO_DEV)) {  in d40_phy_cfg()
88 		dst |= D40_TYPE_TO_EVENT(cfg->dev_type);  in d40_phy_cfg()
90 		if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)  in d40_phy_cfg()
95 	/* Interrupt on end of transfer for destination */  in d40_phy_cfg()
98 	/* Generate interrupt on error */  in d40_phy_cfg()
99 	src |= BIT(D40_SREG_CFG_EIM_POS);  in d40_phy_cfg()
103 	if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {  in d40_phy_cfg()
104 		src |= BIT(D40_SREG_CFG_PHY_PEN_POS);  in d40_phy_cfg()
105 		src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;  in d40_phy_cfg()
107 	if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {  in d40_phy_cfg()
109 		dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;  in d40_phy_cfg()
113 	src |= d40_width_to_bits(cfg->src_info.data_width)  in d40_phy_cfg()
115 	dst |= d40_width_to_bits(cfg->dst_info.data_width)  in d40_phy_cfg()
119 	if (cfg->high_priority) {  in d40_phy_cfg()
120 		src |= BIT(D40_SREG_CFG_PRI_POS);  in d40_phy_cfg()
124 	if (cfg->src_info.big_endian)  in d40_phy_cfg()
125 		src |= BIT(D40_SREG_CFG_LBE_POS);  in d40_phy_cfg()
126 	if (cfg->dst_info.big_endian)  in d40_phy_cfg()
129 	*src_cfg = src;  in d40_phy_cfg()
143 	unsigned int data_width = info->data_width;  in d40_phy_fill_lli()
144 	int psize = info->psize;  in d40_phy_fill_lli()
154 		return -EINVAL;  in d40_phy_fill_lli()
158 		return -EINVAL;  in d40_phy_fill_lli()
161 	lli->reg_elt = (data_size / data_width) << D40_SREG_ELEM_PHY_ECNT_POS;  in d40_phy_fill_lli()
168 		lli->reg_elt |= data_width << D40_SREG_ELEM_PHY_EIDX_POS;  in d40_phy_fill_lli()
171 	lli->reg_ptr = data;  in d40_phy_fill_lli()
172 	lli->reg_cfg = reg_cfg;  in d40_phy_fill_lli()
176 		lli->reg_lnk = BIT(D40_SREG_LNK_PHY_TCP_POS);  in d40_phy_fill_lli()
178 		lli->reg_lnk = next_lli;  in d40_phy_fill_lli()
180 	/* Set/clear interrupt generation on this link item.*/  in d40_phy_fill_lli()
182 		lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS);  in d40_phy_fill_lli()
184 		lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);  in d40_phy_fill_lli()
187 	 * Post link - D40_SREG_LNK_PHY_PRE_POS = 0  in d40_phy_fill_lli()
201 		seg_max -= max_w;  in d40_seg_size()
236 		size_seg = d40_seg_size(size_rest, info->data_width,  in d40_phy_buf_to_lli()
237 					otherinfo->data_width);  in d40_phy_buf_to_lli()
238 		size_rest -= size_seg;  in d40_phy_buf_to_lli()
292 		if (i == sg_len - 1)  in d40_phy_sg_to_lli()
295 		l_phys = ALIGN(lli_phys + (lli - lli_sg) *  in d40_phy_sg_to_lli()
302 			return -EINVAL;  in d40_phy_sg_to_lli()
315 	bool interrupt = flags & LLI_TERM_INT;  in d40_log_lli_link()  local
319 	if (next != -EINVAL) {  in d40_log_lli_link()
324 	if (interrupt) {  in d40_log_lli_link()
325 		lli_dst->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;  in d40_log_lli_link()
326 		lli_dst->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;  in d40_log_lli_link()
329 	lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |  in d40_log_lli_link()
332 	lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |  in d40_log_lli_link()
343 	writel_relaxed(lli_src->lcsp02, &lcpa[0].lcsp0);  in d40_log_lli_lcpa_write()
344 	writel_relaxed(lli_src->lcsp13, &lcpa[0].lcsp1);  in d40_log_lli_lcpa_write()
345 	writel_relaxed(lli_dst->lcsp02, &lcpa[0].lcsp2);  in d40_log_lli_lcpa_write()
346 	writel_relaxed(lli_dst->lcsp13, &lcpa[0].lcsp3);  in d40_log_lli_lcpa_write()
356 	writel_relaxed(lli_src->lcsp02, &lcla[0].lcsp02);  in d40_log_lli_lcla_write()
357 	writel_relaxed(lli_src->lcsp13, &lcla[0].lcsp13);  in d40_log_lli_lcla_write()
358 	writel_relaxed(lli_dst->lcsp02, &lcla[1].lcsp02);  in d40_log_lli_lcla_write()
359 	writel_relaxed(lli_dst->lcsp13, &lcla[1].lcsp13);  in d40_log_lli_lcla_write()
370 	lli->lcsp13 = reg_cfg;  in d40_log_fill_lli()
373 	lli->lcsp02 = ((data_size / data_width) <<  in d40_log_fill_lli()
379 	lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;  in d40_log_fill_lli()
381 	lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;  in d40_log_fill_lli()
384 		lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;  in d40_log_fill_lli()
391 				       u32 lcsp13, /* src or dst*/  in d40_log_buf_to_lli()
403 		size_rest -= size_seg;  in d40_log_buf_to_lli()
422 		      u32 lcsp13, /* src or dst*/  in d40_log_sg_to_lli()