1 // SPDX-License-Identifier: GPL-2.0-or-later
10  * QUICC ENGINE Interrupt Controller
62  * QE interrupt controller internal structure
72 	 * For grouped interrupts sources - the interrupt code as
248 	unsigned int src = irqd_to_hwirq(d);  in qe_ic_unmask_irq()  local
254 	temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);  in qe_ic_unmask_irq()
255 	qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,  in qe_ic_unmask_irq()
256 		    temp | qe_ic_info[src].mask);  in qe_ic_unmask_irq()
264 	unsigned int src = irqd_to_hwirq(d);  in qe_ic_mask_irq()  local
270 	temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);  in qe_ic_mask_irq()
271 	qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,  in qe_ic_mask_irq()
272 		    temp & ~qe_ic_info[src].mask);  in qe_ic_mask_irq()
305 	struct qe_ic *qe_ic = h->host_data;  in qe_ic_host_map()
310 		return -EINVAL;  in qe_ic_host_map()
315 		return -EINVAL;  in qe_ic_host_map()
318 	chip = &qe_ic->hc_irq;  in qe_ic_host_map()
334 /* Return an interrupt vector or 0 if no interrupt is pending. */
341 	/* get the interrupt source vector. */  in qe_ic_get_low_irq()
342 	irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;  in qe_ic_get_low_irq()
347 	return irq_linear_revmap(qe_ic->irqhost, irq);  in qe_ic_get_low_irq()
350 /* Return an interrupt vector or 0 if no interrupt is pending. */
357 	/* get the interrupt source vector. */  in qe_ic_get_high_irq()
358 	irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;  in qe_ic_get_high_irq()
363 	return irq_linear_revmap(qe_ic->irqhost, irq);  in qe_ic_get_high_irq()
375 	if (chip->irq_eoi)  in qe_ic_cascade_low()
376 		chip->irq_eoi(&desc->irq_data);  in qe_ic_cascade_low()
388 	if (chip->irq_eoi)  in qe_ic_cascade_high()
389 		chip->irq_eoi(&desc->irq_data);  in qe_ic_cascade_high()
405 	chip->irq_eoi(&desc->irq_data);  in qe_ic_cascade_muxed_mpic()
410 	struct device *dev = &pdev->dev;  in qe_ic_init()
415 	struct device_node *node = pdev->dev.of_node;  in qe_ic_init()
420 		return -ENODEV;  in qe_ic_init()
425 		return -ENOMEM;  in qe_ic_init()
427 	qe_ic->regs = devm_ioremap(dev, res->start, resource_size(res));  in qe_ic_init()
428 	if (qe_ic->regs == NULL) {  in qe_ic_init()
430 		return -ENODEV;  in qe_ic_init()
433 	qe_ic->hc_irq = qe_ic_irq_chip;  in qe_ic_init()
435 	qe_ic->virq_high = platform_get_irq(pdev, 0);  in qe_ic_init()
436 	qe_ic->virq_low = platform_get_irq(pdev, 1);  in qe_ic_init()
438 	if (qe_ic->virq_low <= 0)  in qe_ic_init()
439 		return -ENODEV;  in qe_ic_init()
441 	if (qe_ic->virq_high > 0 && qe_ic->virq_high != qe_ic->virq_low) {  in qe_ic_init()
449 	qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,  in qe_ic_init()
451 	if (qe_ic->irqhost == NULL) {  in qe_ic_init()
453 		return -ENODEV;  in qe_ic_init()
456 	qe_ic_write(qe_ic->regs, QEIC_CICR, 0);  in qe_ic_init()
458 	irq_set_handler_data(qe_ic->virq_low, qe_ic);  in qe_ic_init()
459 	irq_set_chained_handler(qe_ic->virq_low, low_handler);  in qe_ic_init()
462 		irq_set_handler_data(qe_ic->virq_high, qe_ic);  in qe_ic_init()
463 		irq_set_chained_handler(qe_ic->virq_high, high_handler);  in qe_ic_init()
468 	{ .compatible = "fsl,qe-ic"},
476 		.name		= "qe-ic",