Lines Matching +full:interrupt +full:- +full:src
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * IBM PowerPC 4xx Universal Interrupt Controller
20 #include <linux/interrupt.h>
55 unsigned int src = irqd_to_hwirq(d); in uic_unmask_irq() local
59 sr = 1 << (31-src); in uic_unmask_irq()
60 raw_spin_lock_irqsave(&uic->lock, flags); in uic_unmask_irq()
61 /* ack level-triggered interrupts here */ in uic_unmask_irq()
63 mtdcr(uic->dcrbase + UIC_SR, sr); in uic_unmask_irq()
64 er = mfdcr(uic->dcrbase + UIC_ER); in uic_unmask_irq()
66 mtdcr(uic->dcrbase + UIC_ER, er); in uic_unmask_irq()
67 raw_spin_unlock_irqrestore(&uic->lock, flags); in uic_unmask_irq()
73 unsigned int src = irqd_to_hwirq(d); in uic_mask_irq() local
77 raw_spin_lock_irqsave(&uic->lock, flags); in uic_mask_irq()
78 er = mfdcr(uic->dcrbase + UIC_ER); in uic_mask_irq()
79 er &= ~(1 << (31 - src)); in uic_mask_irq()
80 mtdcr(uic->dcrbase + UIC_ER, er); in uic_mask_irq()
81 raw_spin_unlock_irqrestore(&uic->lock, flags); in uic_mask_irq()
87 unsigned int src = irqd_to_hwirq(d); in uic_ack_irq() local
90 raw_spin_lock_irqsave(&uic->lock, flags); in uic_ack_irq()
91 mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src)); in uic_ack_irq()
92 raw_spin_unlock_irqrestore(&uic->lock, flags); in uic_ack_irq()
98 unsigned int src = irqd_to_hwirq(d); in uic_mask_ack_irq() local
102 sr = 1 << (31-src); in uic_mask_ack_irq()
103 raw_spin_lock_irqsave(&uic->lock, flags); in uic_mask_ack_irq()
104 er = mfdcr(uic->dcrbase + UIC_ER); in uic_mask_ack_irq()
106 mtdcr(uic->dcrbase + UIC_ER, er); in uic_mask_ack_irq()
108 * a level irq will have no effect if the interrupt in uic_mask_ack_irq()
110 * the interrupt is already masked. Therefore in uic_mask_ack_irq()
116 mtdcr(uic->dcrbase + UIC_SR, sr); in uic_mask_ack_irq()
117 raw_spin_unlock_irqrestore(&uic->lock, flags); in uic_mask_ack_irq()
123 unsigned int src = irqd_to_hwirq(d); in uic_set_irq_type() local
146 return -EINVAL; in uic_set_irq_type()
149 mask = ~(1 << (31 - src)); in uic_set_irq_type()
151 raw_spin_lock_irqsave(&uic->lock, flags); in uic_set_irq_type()
152 tr = mfdcr(uic->dcrbase + UIC_TR); in uic_set_irq_type()
153 pr = mfdcr(uic->dcrbase + UIC_PR); in uic_set_irq_type()
154 tr = (tr & mask) | (trigger << (31-src)); in uic_set_irq_type()
155 pr = (pr & mask) | (polarity << (31-src)); in uic_set_irq_type()
157 mtdcr(uic->dcrbase + UIC_PR, pr); in uic_set_irq_type()
158 mtdcr(uic->dcrbase + UIC_TR, tr); in uic_set_irq_type()
159 mtdcr(uic->dcrbase + UIC_SR, ~mask); in uic_set_irq_type()
161 raw_spin_unlock_irqrestore(&uic->lock, flags); in uic_set_irq_type()
178 struct uic *uic = h->host_data; in uic_host_map()
202 int src; in uic_irq_cascade() local
204 raw_spin_lock(&desc->lock); in uic_irq_cascade()
206 chip->irq_mask(idata); in uic_irq_cascade()
208 chip->irq_mask_ack(idata); in uic_irq_cascade()
209 raw_spin_unlock(&desc->lock); in uic_irq_cascade()
211 msr = mfdcr(uic->dcrbase + UIC_MSR); in uic_irq_cascade()
212 if (!msr) /* spurious interrupt */ in uic_irq_cascade()
215 src = 32 - ffs(msr); in uic_irq_cascade()
217 generic_handle_domain_irq(uic->irqhost, src); in uic_irq_cascade()
220 raw_spin_lock(&desc->lock); in uic_irq_cascade()
222 chip->irq_ack(idata); in uic_irq_cascade()
223 if (!irqd_irq_disabled(idata) && chip->irq_unmask) in uic_irq_cascade()
224 chip->irq_unmask(idata); in uic_irq_cascade()
225 raw_spin_unlock(&desc->lock); in uic_irq_cascade()
240 raw_spin_lock_init(&uic->lock); in uic_init_one()
241 indexp = of_get_property(node, "cell-index", &len); in uic_init_one()
244 "cell-index property\n", node); in uic_init_one()
247 uic->index = *indexp; in uic_init_one()
249 dcrreg = of_get_property(node, "dcr-reg", &len); in uic_init_one()
252 "dcr-reg property\n", node); in uic_init_one()
255 uic->dcrbase = *dcrreg; in uic_init_one()
257 uic->irqhost = irq_domain_add_linear(node, NR_UIC_INTS, &uic_host_ops, in uic_init_one()
259 if (! uic->irqhost) in uic_init_one()
262 /* Start with all interrupts disabled, level and non-critical */ in uic_init_one()
263 mtdcr(uic->dcrbase + UIC_ER, 0); in uic_init_one()
264 mtdcr(uic->dcrbase + UIC_CR, 0); in uic_init_one()
265 mtdcr(uic->dcrbase + UIC_TR, 0); in uic_init_one()
267 mtdcr(uic->dcrbase + UIC_SR, 0xffffffff); in uic_init_one()
269 printk ("UIC%d (%d IRQ sources) at DCR 0x%x\n", uic->index, in uic_init_one()
270 NR_UIC_INTS, uic->dcrbase); in uic_init_one()
281 /* First locate and initialize the top-level UIC */ in uic_init_tree()
289 * top-level interrupt controller */ in uic_init_tree()
294 irq_set_default_host(primary_uic->irqhost); in uic_init_tree()
319 /* Return an interrupt vector or 0 if no interrupt is pending. */
323 int src; in uic_get_irq() local
327 msr = mfdcr(primary_uic->dcrbase + UIC_MSR); in uic_get_irq()
328 src = 32 - ffs(msr); in uic_get_irq()
330 return irq_linear_revmap(primary_uic->irqhost, src); in uic_get_irq()