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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Driscv,imsics.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Incoming MSI Controller (IMSIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
15 AIA specification can be found at https://github.com/riscv/riscv-aia.
17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
[all …]
/linux-6.12.1/drivers/gpu/drm/renesas/rcar-du/
Drcar_du_group.c1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Display Unit Channels Pair
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
11 * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
12 * unit, timings generator, ...) and device-global resources (start/stop
19 * modeled as a single device with three CRTCs, two sets of "semi-global"
20 * resources, and a few device-global resources.
23 * counterpart in the DU documentation, that models those semi-global resources.
35 return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg); in rcar_du_group_read()
40 rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data); in rcar_du_group_write()
[all …]
/linux-6.12.1/net/netfilter/
Dnft_set_pipapo.h1 // SPDX-License-Identifier: GPL-2.0-only
8 /* Count of concatenated fields depends on count of 32-bit nftables registers */
18 /* Bits to be grouped together in table buckets depending on set size */
25 #define NFT_PIPAPO_GROUPS_PER_BYTE(f) (BITS_PER_BYTE / (f)->bb)
28 * small group width, and switch to the big group width if the table gets
32 * crossing page boundaries on most architectures (x86-64 and MIPS huge pages,
34 * keeps performance nice in case kvmalloc() gives us non-contiguous areas.
39 #define NFT_PIPAPO_LT_SIZE_LOW NFT_PIPAPO_LT_SIZE_THRESHOLD - \
42 /* Fields are padded to 32 bits in input registers */
44 (round_up((f)->groups / NFT_PIPAPO_GROUPS_PER_BYTE(f), sizeof(u32)))
[all …]
Dnft_set_pipapo.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2019-2020 Red Hat GmbH
15 * -------
17 * Match packet bytes against entries composed of ranged or non-ranged packet
22 * --- fields --->
33 * ------------------
36 * relies on the consideration that every contiguous range in a space of b bits
40 * Classification against a number of entries, that require matching given bits
41 * of a packet field, is performed by grouping those bits in sets of arbitrary
42 * size, and classifying packet bits one group at a time.
[all …]
/linux-6.12.1/drivers/platform/mellanox/
Dmlxreg-io.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/hwmon-sysfs.h>
23 * struct mlxreg_io_priv_data - driver's private data:
30 * @group: sysfs attribute group;
31 * @groups: list of sysfs attribute group for hwmon registration;
41 struct attribute_group group; member
53 ret = regmap_read(regmap, data->reg, regval); in mlxreg_io_get_reg()
59 * bits, bit sequence, bits in few registers For the first kind field in mlxreg_io_get_reg()
60 * mask indicates which bits are not related and field bit is set zero. in mlxreg_io_get_reg()
62 * with all bits one. No special handling for such kind of attributes - in mlxreg_io_get_reg()
[all …]
/linux-6.12.1/drivers/irqchip/
Dirq-riscv-aplic-msi.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/irqchip/riscv-aplic.h>
13 #include <linux/irqchip/riscv-imsic.h>
21 #include "irq-riscv-aplic-main.h"
43 * The section "4.9.2 Special consideration for level-sensitive interrupt in aplic_msi_irq_retrigger_level()
44 * sources" of the RISC-V AIA specification says: in aplic_msi_irq_retrigger_level()
52 writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE); in aplic_msi_irq_retrigger_level()
60 * EOI handling is required only for level-triggered interrupts in aplic_msi_irq_eoi()
73 * Updating sourcecfg register for level-triggered interrupts in aplic_msi_irq_set_type()
84 struct aplic_msicfg *mc = &priv->msicfg; in aplic_msi_write_msg()
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Dirq-riscv-imsic-state.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "riscv-imsic: " fmt
22 #include "irq-riscv-imsic-state.h"
63 return imsic ? &imsic->global : NULL; in imsic_get_global_config()
74 imask = BIT(id & (__riscv_xlen - 1)); in __imsic_eix_read_clear()
102 * are XLEN-wide and we must not touch IDs which in __imsic_eix_update()
106 for (i = id & (__riscv_xlen - 1); id < last_id && i < __riscv_xlen; i++) { in __imsic_eix_update()
133 lockdep_assert_held(&lpriv->lock); in __imsic_local_sync()
135 for_each_set_bit(i, lpriv->dirty_bitmap, imsic->global.nr_ids + 1) { in __imsic_local_sync()
138 vec = &lpriv->vectors[i]; in __imsic_local_sync()
[all …]
/linux-6.12.1/mm/
Dpercpu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * mm/percpu.c - percpu memory allocator
13 * a 1-to-1 mapping for units to possible cpus. These units are grouped
17 * ------------------- ------------------- ------------
19 * ------------------- ...... ------------------- .... ------------
23 * c1:u1, c1:u2, etc. On NUMA machines, the mapping may be non-linear
35 * linker. The reserved section, if non-zero, primarily manages static
40 * memcg-awareness. To make a percpu allocation memcg-aware the __GFP_ACCOUNT
41 * flag should be passed. All memcg-aware allocations are sharing one set
51 * the page's index. Lastly, units are lazily backed and grow in unison.
[all …]
/linux-6.12.1/drivers/pinctrl/meson/
Dpinctrl-meson.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 * struct meson_pmx_group - a pinmux group
22 * @name: group name
23 * @pins: pins in the group
24 * @num_pins: number of pins in the group
25 * @is_gpio: whether the group is a single GPIO group
26 * @reg: register offset for the group in the domain mux registers
27 * @bit bit index enabling the group
28 * @domain: index of the domain this group belongs to
38 * struct meson_pmx_func - a pinmux function
[all …]
/linux-6.12.1/tools/perf/
Ddesign.txt3 ------------------------------
7 as instructions executed, cachemisses suffered, or branches mis-predicted -
9 trigger interrupts when a threshold number of events have passed - and can
15 provides "virtual" 64-bit counters, regardless of the width of the
41 * 7 bits are an event type and the rest of the bits are the event
53 exclusive : 1, /* only group on PMU */
72 is divided into 3 bit-fields:
75 type: 7 bits (next most significant) 0x7f00_0000_0000_0000
76 event_id: 56 bits (least significant) 0x00ff_ffff_ffff_ffff
79 specified by the remaining 63 bits of event_config. The encoding is
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/linux-6.12.1/arch/mips/include/asm/octeon/
Dcvmx-pow.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 * New, starting with SDK 1.7.0, cvmx-pow supports a number of
36 * enabled. For example, cvmx-pow will check for the following
38 * - Requesting a POW operation with an active tag switch in
40 * - Waiting for a tag switch to complete for an excessively
43 * - Illegal tag switches from NULL_NULL.
44 * - Illegal tag switches from NULL.
45 * - Illegal deschedule request.
[all …]
/linux-6.12.1/drivers/pinctrl/ti/
Dpinctrl-ti-iodelay.c5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
23 #include <linux/pinctrl/pinconf-generic.h>
30 #define DRIVER_NAME "ti-iodelay"
33 * struct ti_iodelay_reg_data - Describes the registers for the iodelay instance
34 * @signature_mask: CONFIG_REG mask for the signature bits (see TRM)
36 * @lock_mask: CONFIG_REG mask for the lock bits (see TRM)
37 * @lock_val: CONFIG_REG lock value for the lock bits (see TRM)
38 * @unlock_val:CONFIG_REG unlock value for the lock bits (see TRM)
89 * struct ti_iodelay_reg_values - Computed io_reg configuration values (see TRM)
112 * struct ti_iodelay_cfg - Description of each configuration parameters
[all …]
/linux-6.12.1/tools/perf/trace/beauty/include/uapi/linux/
Dvhost.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 /* Userspace interface for in-kernel virtio accelerators. */
18 #define VHOST_FILE_UNBIND -1
24 /* Features bitmask for forward compatibility. Transport bits are used for
76 /* Get accessor: reads index, writes value in num */
80 * or VHOST_VRING_BIG_ENDIAN (other values return -EINVAL).
82 * returns -EBUSY.
130 * used for transmit. Pass fd -1 to unbind from the socket and the transmit
152 * the device id defined in virtio-spec.
155 /* Get and set the status. The status bits follow the same definition
[all …]
/linux-6.12.1/include/uapi/linux/
Dvhost.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 /* Userspace interface for in-kernel virtio accelerators. */
18 #define VHOST_FILE_UNBIND -1
24 /* Features bitmask for forward compatibility. Transport bits are used for
76 /* Get accessor: reads index, writes value in num */
80 * or VHOST_VRING_BIG_ENDIAN (other values return -EINVAL).
82 * returns -EBUSY.
130 * used for transmit. Pass fd -1 to unbind from the socket and the transmit
152 * the device id defined in virtio-spec.
155 /* Get and set the status. The status bits follow the same definition
[all …]
/linux-6.12.1/fs/ocfs2/
Docfs2_fs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * On-disk structures for OCFS2.
59 ( OCFS2_SB(sb)->s_feature_compat & (mask) )
61 ( OCFS2_SB(sb)->s_feature_ro_compat & (mask) )
63 ( OCFS2_SB(sb)->s_feature_incompat & (mask) )
65 OCFS2_SB(sb)->s_feature_compat |= (mask)
67 OCFS2_SB(sb)->s_feature_ro_compat |= (mask)
69 OCFS2_SB(sb)->s_feature_incompat |= (mask)
71 OCFS2_SB(sb)->s_feature_compat &= ~(mask)
73 OCFS2_SB(sb)->s_feature_ro_compat &= ~(mask)
[all …]
/linux-6.12.1/include/linux/
Dvdpa.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 * struct vdpa_callback - vDPA callback definition.
30 * struct vdpa_notification_area - vDPA notification area
40 * struct vdpa_vq_state_split - vDPA split virtqueue state
41 * @avail_index: available index
48 * struct vdpa_vq_state_packed - vDPA packed virtqueue state
50 * @last_avail_idx: device available index
52 * @last_used_idx: used index
71 * struct vdpa_device - representation of a vDPA device
79 * @index: device index
[all …]
/linux-6.12.1/drivers/pinctrl/renesas/
Dpinctrl-rzv2m.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/pinctrl/pinconf-generic.h>
28 #include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
34 #define DRV_NAME "pinctrl-rzv2m"
37 * Use 16 lower bits [15:0] for pin identifier
38 * Use 16 higher bits [31:16] for pin mux function
60 * n indicates number of pins in the port, a is the register index
71 * BIT(31) indicates dedicated pin, b is the register bits (b * 16)
148 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 1); in rzv2m_pinctrl_set_pfc_mode()
149 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 1); in rzv2m_pinctrl_set_pfc_mode()
[all …]
/linux-6.12.1/drivers/iio/adc/
Dti-tsc2046.c1 // SPDX-License-Identifier: GPL-2.0
29 * - rate limiting:
31 * - hrtimer:
61 * conversion has 12-bit resolution, whereas with this bit high, the next
62 * conversion has 8-bit resolution. This driver is optimized for 12-bit mode.
68 * SER/DFR - The SER/DFR bit controls the reference mode, either single-ended
75 * auto-wake/suspend mode. In most case this bits should stay zero.
110 /* Group offset within the SPI RX buffer */
114 * within same group.
185 #define TI_TSC2046_V_CHAN(index, bits, name) \ argument
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/linux-6.12.1/Documentation/filesystems/ext4/
Dinodes.rst1 .. SPDX-License-Identifier: GPL-2.0
3 Index Nodes
4 -----------
15 links and is in general more seek-happy than ext4 due to its simpler
21 block group containing an inode can be calculated as
22 ``(inode_number - 1) / sb.s_inodes_per_group``, and the offset into the
23 group's table is ``(inode_number - 1) % sb.s_inodes_per_group``. There
31 .. list-table::
33 :header-rows: 1
36 * - Offset
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/linux-6.12.1/tools/testing/selftests/kvm/lib/aarch64/
Dvgic.c1 // SPDX-License-Identifier: GPL-2.0
19 * vGIC-v3 default host setup
22 * vm - KVM VM
23 * nr_vcpus - Number of vCPUs supported by this VM
27 * Return: GIC file-descriptor or negative error code upon failure
29 * The function creates a vGIC-v3 device and maps the distributor and
46 list_for_each(iter, &vm->vcpus) in vgic_v3_setup()
65 nr_gic_pages = vm_calc_num_guest_pages(vm->mode, KVM_VGIC_V3_DIST_SIZE); in vgic_v3_setup()
72 nr_gic_pages = vm_calc_num_guest_pages(vm->mode, in vgic_v3_setup()
86 uint64_t index = intid % 32; in _kvm_irq_set_level_info() local
[all …]
/linux-6.12.1/Documentation/admin-guide/device-mapper/
Dswitch.rst2 dm-switch
5 The device-mapper switch target creates a device that supports an
6 arbitrary mapping of fixed-size regions of I/O across a fixed set of
11 number of fixed-sized address regions but there is no simple pattern
13 dm-stripe.
16 ----------
19 frameless architecture. In this architecture, the storage group
24 The storage group exposes a single target discovery portal, no matter
34 the storage group and initiators. In a multipathing configuration, it
42 A device-mapper table already lets you map different regions of a
[all …]
/linux-6.12.1/drivers/pinctrl/qcom/
Dpinctrl-msm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
38 * struct msm_pingroup - Qualcomm pingroup definition
39 * @grp: Generic data of the pin group (name and pins)
41 * this group. The index of the selected function is used
45 * @ctl_reg: Offset of the register holding control bits for this group.
46 * @io_reg: Offset of the register holding input/output bits for this group.
47 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits.
48 * @intr_status_reg: Offset of the register holding the status bits for this group.
50 * from this group.
58 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group.
[all …]
/linux-6.12.1/fs/jfs/
Djfs_dmap.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) International Business Machines Corp., 2000-2002
12 #define LEAFIND (64+16+4+1) /* index of 1st leaf of a dmap tree */
24 #define ROOT 0 /* index of the root of a tree */
25 #define NOFREE ((s8) -1) /* no blocks free */
66 * - the number of dmaps preceding it
67 * - the number of L0 pages preceding its L0 page
68 * - the number of L1 pages preceding its L1 page
69 * - 3 is added to account for the L2, L1, and L0 page for this dmap
70 * - 1 is added to account for the control page of the map.
[all …]
/linux-6.12.1/include/linux/irqchip/
Driscv-imsic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
50 * XLEN-1 12 0
52 * -------------------------------------------------------------
53 * |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
54 * -------------------------------------------------------------
57 /* Bits representing Guest index, HART index, and Group index */
72 /* Per-CPU IMSIC addresses */
/linux-6.12.1/drivers/crypto/marvell/octeontx2/
Dotx2_cptpf_ucode.h1 /* SPDX-License-Identifier: GPL-2.0-only
16 * IE and SE engines can be attached to the same engine group.
35 OTX2_CPT_AE_UC_TYPE = 1, /* AE-MAIN */
36 OTX2_CPT_SE_UC_TYPE1 = 20,/* SE-MAIN - combination of 21 and 22 */
42 OTX2_CPT_IE_UC_TYPE1 = 30, /* IE-MAIN - combination of 31 and 32 */
51 unsigned long bits[OTX2_CPT_ENGS_BITMASK_LEN]; member
104 /* Engines reserved to an engine group */
116 * group which mirrors another engine group
119 * index of engine group which is mirrored by this
120 * group, set only for engine group which mirrors
[all …]

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