Lines Matching +full:group +full:- +full:index +full:- +full:bits
1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/pinctrl/pinconf-generic.h>
28 #include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
34 #define DRV_NAME "pinctrl-rzv2m"
37 * Use 16 lower bits [15:0] for pin identifier
38 * Use 16 higher bits [31:16] for pin mux function
60 * n indicates number of pins in the port, a is the register index
71 * BIT(31) indicates dedicated pin, b is the register bits (b * 16)
148 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 1); in rzv2m_pinctrl_set_pfc_mode()
149 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 1); in rzv2m_pinctrl_set_pfc_mode()
151 /* Select the function and set the write enable bits */ in rzv2m_pinctrl_set_pfc_mode()
152 addr = pctrl->base + PFSEL(port) + (pin / 4) * 4; in rzv2m_pinctrl_set_pfc_mode()
156 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 0); in rzv2m_pinctrl_set_pfc_mode()
157 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 0); in rzv2m_pinctrl_set_pfc_mode()
167 struct group_desc *group; in rzv2m_pinctrl_set_mux() local
172 return -EINVAL; in rzv2m_pinctrl_set_mux()
173 group = pinctrl_generic_get_group(pctldev, group_selector); in rzv2m_pinctrl_set_mux()
174 if (!group) in rzv2m_pinctrl_set_mux()
175 return -EINVAL; in rzv2m_pinctrl_set_mux()
177 psel_val = func->data; in rzv2m_pinctrl_set_mux()
178 pins = group->grp.pins; in rzv2m_pinctrl_set_mux()
180 for (i = 0; i < group->grp.npins; i++) { in rzv2m_pinctrl_set_mux()
181 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", in rzv2m_pinctrl_set_mux()
201 return -ENOMEM; in rzv2m_map_add_config()
203 map->type = type; in rzv2m_map_add_config()
204 map->data.configs.group_or_pin = group_or_pin; in rzv2m_map_add_config()
205 map->data.configs.configs = cfgs; in rzv2m_map_add_config()
206 map->data.configs.num_configs = num_configs; in rzv2m_map_add_config()
216 unsigned int *index) in rzv2m_dt_subnode_to_map() argument
224 unsigned int idx = *index; in rzv2m_dt_subnode_to_map()
236 num_pinmux = pinmux->length / sizeof(u32); in rzv2m_dt_subnode_to_map()
239 if (ret == -EINVAL) { in rzv2m_dt_subnode_to_map()
242 dev_err(pctrl->dev, "Invalid pins list in DT\n"); in rzv2m_dt_subnode_to_map()
252 dev_err(pctrl->dev, in rzv2m_dt_subnode_to_map()
254 return -EINVAL; in rzv2m_dt_subnode_to_map()
262 dev_err(pctrl->dev, "DT node must contain a config\n"); in rzv2m_dt_subnode_to_map()
263 ret = -ENODEV; in rzv2m_dt_subnode_to_map()
275 ret = -ENOMEM; in rzv2m_dt_subnode_to_map()
295 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); in rzv2m_dt_subnode_to_map()
296 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), in rzv2m_dt_subnode_to_map()
298 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); in rzv2m_dt_subnode_to_map()
300 ret = -ENOMEM; in rzv2m_dt_subnode_to_map()
316 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", in rzv2m_dt_subnode_to_map()
319 ret = -ENOMEM; in rzv2m_dt_subnode_to_map()
323 name = np->name; in rzv2m_dt_subnode_to_map()
326 mutex_lock(&pctrl->mutex); in rzv2m_dt_subnode_to_map()
328 /* Register a single pin group listing all the pins we read from DT */ in rzv2m_dt_subnode_to_map()
336 * Register a single group function where the 'data' is an array PSEL in rzv2m_dt_subnode_to_map()
346 mutex_unlock(&pctrl->mutex); in rzv2m_dt_subnode_to_map()
349 maps[idx].data.mux.group = name; in rzv2m_dt_subnode_to_map()
353 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); in rzv2m_dt_subnode_to_map()
360 mutex_unlock(&pctrl->mutex); in rzv2m_dt_subnode_to_map()
362 *index = idx; in rzv2m_dt_subnode_to_map()
390 unsigned int index; in rzv2m_dt_node_to_map() local
395 index = 0; in rzv2m_dt_node_to_map()
399 num_maps, &index); in rzv2m_dt_node_to_map()
406 num_maps, &index); in rzv2m_dt_node_to_map()
414 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); in rzv2m_dt_node_to_map()
415 ret = -EINVAL; in rzv2m_dt_node_to_map()
430 if (bit >= pincount || port >= pctrl->data->n_port_pins) in rzv2m_validate_gpio_pin()
431 return -EINVAL; in rzv2m_validate_gpio_pin()
433 data = pctrl->data->port_pin_configs[port]; in rzv2m_validate_gpio_pin()
435 return -EINVAL; in rzv2m_validate_gpio_pin()
443 void __iomem *addr = pctrl->base + offset; in rzv2m_rmw_pin_config()
447 spin_lock_irqsave(&pctrl->lock, flags); in rzv2m_rmw_pin_config()
450 spin_unlock_irqrestore(&pctrl->lock, flags); in rzv2m_rmw_pin_config()
459 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzv2m_pinctrl_pinconf_get()
460 unsigned int *pin_data = pin->drv_data; in rzv2m_pinctrl_pinconf_get()
468 return -EINVAL; in rzv2m_pinctrl_pinconf_get()
480 return -EINVAL; in rzv2m_pinctrl_pinconf_get()
490 return -EINVAL; in rzv2m_pinctrl_pinconf_get()
492 /* PUPD uses 2-bits per pin */ in rzv2m_pinctrl_pinconf_get()
495 switch ((readl(pctrl->base + PUPD(port)) >> bit) & PUPD_MASK) { in rzv2m_pinctrl_pinconf_get()
507 return -EINVAL; in rzv2m_pinctrl_pinconf_get()
513 return -EINVAL; in rzv2m_pinctrl_pinconf_get()
515 /* DRV uses 2-bits per pin */ in rzv2m_pinctrl_pinconf_get()
518 val = (readl(pctrl->base + DRV(port)) >> bit) & DRV_MASK; in rzv2m_pinctrl_pinconf_get()
535 return -EINVAL; in rzv2m_pinctrl_pinconf_get()
542 return -EINVAL; in rzv2m_pinctrl_pinconf_get()
544 arg = readl(pctrl->base + SR(port)) & BIT(bit); in rzv2m_pinctrl_pinconf_get()
548 return -ENOTSUPP; in rzv2m_pinctrl_pinconf_get()
562 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzv2m_pinctrl_pinconf_set()
563 unsigned int *pin_data = pin->drv_data; in rzv2m_pinctrl_pinconf_set()
572 return -EINVAL; in rzv2m_pinctrl_pinconf_set()
584 return -EINVAL; in rzv2m_pinctrl_pinconf_set()
594 return -EINVAL; in rzv2m_pinctrl_pinconf_set()
596 /* PUPD uses 2-bits per pin */ in rzv2m_pinctrl_pinconf_set()
616 unsigned int index; in rzv2m_pinctrl_pinconf_set() local
619 return -EINVAL; in rzv2m_pinctrl_pinconf_set()
636 return -EINVAL; in rzv2m_pinctrl_pinconf_set()
639 for (index = 0; index < 4; index++) { in rzv2m_pinctrl_pinconf_set()
640 if (arg == drv_strengths[index]) in rzv2m_pinctrl_pinconf_set()
643 if (index >= 4) in rzv2m_pinctrl_pinconf_set()
644 return -EINVAL; in rzv2m_pinctrl_pinconf_set()
646 /* DRV uses 2-bits per pin */ in rzv2m_pinctrl_pinconf_set()
649 rzv2m_rmw_pin_config(pctrl, DRV(port), bit, DRV_MASK, index); in rzv2m_pinctrl_pinconf_set()
657 return -EINVAL; in rzv2m_pinctrl_pinconf_set()
659 rzv2m_writel_we(pctrl->base + SR(port), bit, !arg); in rzv2m_pinctrl_pinconf_set()
664 return -EOPNOTSUPP; in rzv2m_pinctrl_pinconf_set()
672 unsigned int group, in rzv2m_pinctrl_pinconf_group_set() argument
680 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); in rzv2m_pinctrl_pinconf_group_set()
695 unsigned int group, in rzv2m_pinctrl_pinconf_group_get() argument
702 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); in rzv2m_pinctrl_pinconf_group_get()
713 return -EOPNOTSUPP; in rzv2m_pinctrl_pinconf_group_get()
765 rzv2m_writel_we(pctrl->base + OE(port), bit, output); in rzv2m_gpio_set_direction()
766 rzv2m_writel_we(pctrl->base + IE(port), bit, !output); in rzv2m_gpio_set_direction()
775 if (!(readl(pctrl->base + IE(port)) & BIT(bit))) in rzv2m_gpio_get_direction()
800 rzv2m_writel_we(pctrl->base + DO(port), bit, !!value); in rzv2m_gpio_set()
824 return !!(readl(pctrl->base + DI(port)) & BIT(bit)); in rzv2m_gpio_get()
826 return !!(readl(pctrl->base + DO(port)) & BIT(bit)); in rzv2m_gpio_get()
931 struct device_node *np = pctrl->dev->of_node; in rzv2m_gpio_register()
932 struct gpio_chip *chip = &pctrl->gpio_chip; in rzv2m_gpio_register()
933 const char *name = dev_name(pctrl->dev); in rzv2m_gpio_register()
937 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); in rzv2m_gpio_register()
939 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); in rzv2m_gpio_register()
944 of_args.args[2] != pctrl->data->n_port_pins) { in rzv2m_gpio_register()
945 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); in rzv2m_gpio_register()
946 return -EINVAL; in rzv2m_gpio_register()
949 chip->names = pctrl->data->port_pins; in rzv2m_gpio_register()
950 chip->request = rzv2m_gpio_request; in rzv2m_gpio_register()
951 chip->free = rzv2m_gpio_free; in rzv2m_gpio_register()
952 chip->get_direction = rzv2m_gpio_get_direction; in rzv2m_gpio_register()
953 chip->direction_input = rzv2m_gpio_direction_input; in rzv2m_gpio_register()
954 chip->direction_output = rzv2m_gpio_direction_output; in rzv2m_gpio_register()
955 chip->get = rzv2m_gpio_get; in rzv2m_gpio_register()
956 chip->set = rzv2m_gpio_set; in rzv2m_gpio_register()
957 chip->label = name; in rzv2m_gpio_register()
958 chip->parent = pctrl->dev; in rzv2m_gpio_register()
959 chip->owner = THIS_MODULE; in rzv2m_gpio_register()
960 chip->base = -1; in rzv2m_gpio_register()
961 chip->ngpio = of_args.args[2]; in rzv2m_gpio_register()
963 pctrl->gpio_range.id = 0; in rzv2m_gpio_register()
964 pctrl->gpio_range.pin_base = 0; in rzv2m_gpio_register()
965 pctrl->gpio_range.base = 0; in rzv2m_gpio_register()
966 pctrl->gpio_range.npins = chip->ngpio; in rzv2m_gpio_register()
967 pctrl->gpio_range.name = chip->label; in rzv2m_gpio_register()
968 pctrl->gpio_range.gc = chip; in rzv2m_gpio_register()
969 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); in rzv2m_gpio_register()
971 dev_err(pctrl->dev, "failed to add GPIO controller\n"); in rzv2m_gpio_register()
975 dev_dbg(pctrl->dev, "Registered gpio controller\n"); in rzv2m_gpio_register()
987 pctrl->desc.name = DRV_NAME; in rzv2m_pinctrl_register()
988 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; in rzv2m_pinctrl_register()
989 pctrl->desc.pctlops = &rzv2m_pinctrl_pctlops; in rzv2m_pinctrl_register()
990 pctrl->desc.pmxops = &rzv2m_pinctrl_pmxops; in rzv2m_pinctrl_register()
991 pctrl->desc.confops = &rzv2m_pinctrl_confops; in rzv2m_pinctrl_register()
992 pctrl->desc.owner = THIS_MODULE; in rzv2m_pinctrl_register()
994 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); in rzv2m_pinctrl_register()
996 return -ENOMEM; in rzv2m_pinctrl_register()
998 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, in rzv2m_pinctrl_register()
1001 return -ENOMEM; in rzv2m_pinctrl_register()
1003 pctrl->pins = pins; in rzv2m_pinctrl_register()
1004 pctrl->desc.pins = pins; in rzv2m_pinctrl_register()
1006 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { in rzv2m_pinctrl_register()
1008 pins[i].name = pctrl->data->port_pins[i]; in rzv2m_pinctrl_register()
1011 pin_data[i] = pctrl->data->port_pin_configs[j]; in rzv2m_pinctrl_register()
1015 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzv2m_pinctrl_register()
1016 unsigned int index = pctrl->data->n_port_pins + i; in rzv2m_pinctrl_register() local
1018 pins[index].number = index; in rzv2m_pinctrl_register()
1019 pins[index].name = pctrl->data->dedicated_pins[i].name; in rzv2m_pinctrl_register()
1020 pin_data[index] = pctrl->data->dedicated_pins[i].config; in rzv2m_pinctrl_register()
1021 pins[index].drv_data = &pin_data[index]; in rzv2m_pinctrl_register()
1024 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, in rzv2m_pinctrl_register()
1025 &pctrl->pctl); in rzv2m_pinctrl_register()
1027 dev_err(pctrl->dev, "pinctrl registration failed\n"); in rzv2m_pinctrl_register()
1031 ret = pinctrl_enable(pctrl->pctl); in rzv2m_pinctrl_register()
1033 dev_err(pctrl->dev, "pinctrl enable failed\n"); in rzv2m_pinctrl_register()
1039 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); in rzv2m_pinctrl_register()
1052 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in rzv2m_pinctrl_probe()
1054 return -ENOMEM; in rzv2m_pinctrl_probe()
1056 pctrl->dev = &pdev->dev; in rzv2m_pinctrl_probe()
1058 pctrl->data = of_device_get_match_data(&pdev->dev); in rzv2m_pinctrl_probe()
1059 if (!pctrl->data) in rzv2m_pinctrl_probe()
1060 return -EINVAL; in rzv2m_pinctrl_probe()
1062 pctrl->base = devm_platform_ioremap_resource(pdev, 0); in rzv2m_pinctrl_probe()
1063 if (IS_ERR(pctrl->base)) in rzv2m_pinctrl_probe()
1064 return PTR_ERR(pctrl->base); in rzv2m_pinctrl_probe()
1066 clk = devm_clk_get_enabled(pctrl->dev, NULL); in rzv2m_pinctrl_probe()
1068 return dev_err_probe(pctrl->dev, PTR_ERR(clk), in rzv2m_pinctrl_probe()
1071 spin_lock_init(&pctrl->lock); in rzv2m_pinctrl_probe()
1072 mutex_init(&pctrl->mutex); in rzv2m_pinctrl_probe()
1080 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); in rzv2m_pinctrl_probe()
1094 .compatible = "renesas,r9a09g011-pinctrl",