Lines Matching +full:group +full:- +full:index +full:- +full:bits
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
23 #include <linux/pinctrl/pinconf-generic.h>
30 #define DRIVER_NAME "ti-iodelay"
33 * struct ti_iodelay_reg_data - Describes the registers for the iodelay instance
34 * @signature_mask: CONFIG_REG mask for the signature bits (see TRM)
36 * @lock_mask: CONFIG_REG mask for the lock bits (see TRM)
37 * @lock_val: CONFIG_REG lock value for the lock bits (see TRM)
38 * @unlock_val:CONFIG_REG unlock value for the lock bits (see TRM)
89 * struct ti_iodelay_reg_values - Computed io_reg configuration values (see TRM)
112 * struct ti_iodelay_cfg - Description of each configuration parameters
124 * struct ti_iodelay_pingroup - Structure that describes one group
127 * @config: pinconf "Config" - currently a dummy value
136 * struct ti_iodelay_device - Represents information for a iodelay instance
162 * ti_iodelay_extract() - extract bits for a field
174 * ti_iodelay_compute_dpe() - Compute equation for delay parameter
191 /* Truncate result back to 32 bits */ in ti_iodelay_compute_dpe()
196 * ti_iodelay_pinconf_set() - Configure the pin configuration
212 const struct ti_iodelay_reg_data *reg = iod->reg_data; in ti_iodelay_pinconf_set()
213 struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values; in ti_iodelay_pinconf_set()
214 struct device *dev = iod->dev; in ti_iodelay_pinconf_set()
223 g_delay_coarse = cfg->g_delay / 920; in ti_iodelay_pinconf_set()
224 g_delay_fine = ((cfg->g_delay % 920) * 10) / 60; in ti_iodelay_pinconf_set()
226 a_delay_coarse = cfg->a_delay / ival->cdpe; in ti_iodelay_pinconf_set()
227 a_delay_fine = ((cfg->a_delay % ival->cdpe) * 10) / ival->fdpe; in ti_iodelay_pinconf_set()
233 total_delay = c_elements * ival->cdpe + f_elements * ival->fdpe; in ti_iodelay_pinconf_set()
234 c_elements = total_delay / ival->cdpe; in ti_iodelay_pinconf_set()
235 f_elements = (total_delay % ival->cdpe) / ival->fdpe; in ti_iodelay_pinconf_set()
238 reg_mask = reg->signature_mask; in ti_iodelay_pinconf_set()
239 reg_val = reg->signature_value << __ffs(reg->signature_mask); in ti_iodelay_pinconf_set()
241 reg_mask |= reg->binary_data_coarse_mask; in ti_iodelay_pinconf_set()
242 tmp_val = c_elements << __ffs(reg->binary_data_coarse_mask); in ti_iodelay_pinconf_set()
243 if (tmp_val & ~reg->binary_data_coarse_mask) { in ti_iodelay_pinconf_set()
246 tmp_val &= reg->binary_data_coarse_mask; in ti_iodelay_pinconf_set()
250 reg_mask |= reg->binary_data_fine_mask; in ti_iodelay_pinconf_set()
251 tmp_val = f_elements << __ffs(reg->binary_data_fine_mask); in ti_iodelay_pinconf_set()
252 if (tmp_val & ~reg->binary_data_fine_mask) { in ti_iodelay_pinconf_set()
255 tmp_val &= reg->binary_data_fine_mask; in ti_iodelay_pinconf_set()
260 * NOTE: we leave the iodelay values unlocked - this is to work around in ti_iodelay_pinconf_set()
265 reg_mask |= reg->lock_mask; in ti_iodelay_pinconf_set()
266 reg_val |= reg->unlock_val << __ffs(reg->lock_mask); in ti_iodelay_pinconf_set()
267 r = regmap_update_bits(iod->regmap, cfg->offset, reg_mask, reg_val); in ti_iodelay_pinconf_set()
270 cfg->offset, cfg->a_delay, cfg->g_delay, c_elements, in ti_iodelay_pinconf_set()
277 * ti_iodelay_pinconf_deinit_dev() - deinit the iodelay device
285 const struct ti_iodelay_reg_data *reg = iod->reg_data; in ti_iodelay_pinconf_deinit_dev()
288 regmap_update_bits(iod->regmap, reg->reg_global_lock_offset, in ti_iodelay_pinconf_deinit_dev()
289 reg->global_lock_mask, reg->global_lock_val); in ti_iodelay_pinconf_deinit_dev()
293 * ti_iodelay_pinconf_init_dev() - Initialize IODelay device
302 const struct ti_iodelay_reg_data *reg = iod->reg_data; in ti_iodelay_pinconf_init_dev()
303 struct device *dev = iod->dev; in ti_iodelay_pinconf_init_dev()
304 struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values; in ti_iodelay_pinconf_init_dev()
309 r = regmap_update_bits(iod->regmap, reg->reg_global_lock_offset, in ti_iodelay_pinconf_init_dev()
310 reg->global_lock_mask, reg->global_unlock_val); in ti_iodelay_pinconf_init_dev()
314 r = devm_add_action_or_reset(iod->dev, ti_iodelay_pinconf_deinit_dev, in ti_iodelay_pinconf_init_dev()
320 r = regmap_read(iod->regmap, reg->reg_refclk_offset, &val); in ti_iodelay_pinconf_init_dev()
323 ival->ref_clk_period = ti_iodelay_extract(val, reg->refclk_period_mask); in ti_iodelay_pinconf_init_dev()
324 dev_dbg(dev, "refclk_period=0x%04x\n", ival->ref_clk_period); in ti_iodelay_pinconf_init_dev()
326 r = regmap_read(iod->regmap, reg->reg_coarse_offset, &val); in ti_iodelay_pinconf_init_dev()
329 ival->coarse_ref_count = in ti_iodelay_pinconf_init_dev()
330 ti_iodelay_extract(val, reg->coarse_ref_count_mask); in ti_iodelay_pinconf_init_dev()
331 ival->coarse_delay_count = in ti_iodelay_pinconf_init_dev()
332 ti_iodelay_extract(val, reg->coarse_delay_count_mask); in ti_iodelay_pinconf_init_dev()
333 if (!ival->coarse_delay_count) { in ti_iodelay_pinconf_init_dev()
336 return -EINVAL; in ti_iodelay_pinconf_init_dev()
338 ival->cdpe = ti_iodelay_compute_dpe(ival->ref_clk_period, in ti_iodelay_pinconf_init_dev()
339 ival->coarse_ref_count, in ti_iodelay_pinconf_init_dev()
340 ival->coarse_delay_count, 88); in ti_iodelay_pinconf_init_dev()
341 if (!ival->cdpe) { in ti_iodelay_pinconf_init_dev()
343 ival->ref_clk_period, ival->coarse_ref_count, in ti_iodelay_pinconf_init_dev()
344 ival->coarse_delay_count); in ti_iodelay_pinconf_init_dev()
345 return -EINVAL; in ti_iodelay_pinconf_init_dev()
347 dev_dbg(iod->dev, "coarse: ref=0x%04x delay=0x%04x cdpe=0x%08x\n", in ti_iodelay_pinconf_init_dev()
348 ival->coarse_ref_count, ival->coarse_delay_count, ival->cdpe); in ti_iodelay_pinconf_init_dev()
350 r = regmap_read(iod->regmap, reg->reg_fine_offset, &val); in ti_iodelay_pinconf_init_dev()
353 ival->fine_ref_count = in ti_iodelay_pinconf_init_dev()
354 ti_iodelay_extract(val, reg->fine_ref_count_mask); in ti_iodelay_pinconf_init_dev()
355 ival->fine_delay_count = in ti_iodelay_pinconf_init_dev()
356 ti_iodelay_extract(val, reg->fine_delay_count_mask); in ti_iodelay_pinconf_init_dev()
357 if (!ival->fine_delay_count) { in ti_iodelay_pinconf_init_dev()
360 return -EINVAL; in ti_iodelay_pinconf_init_dev()
362 ival->fdpe = ti_iodelay_compute_dpe(ival->ref_clk_period, in ti_iodelay_pinconf_init_dev()
363 ival->fine_ref_count, in ti_iodelay_pinconf_init_dev()
364 ival->fine_delay_count, 264); in ti_iodelay_pinconf_init_dev()
365 if (!ival->fdpe) { in ti_iodelay_pinconf_init_dev()
367 ival->ref_clk_period, ival->fine_ref_count, in ti_iodelay_pinconf_init_dev()
368 ival->fine_delay_count); in ti_iodelay_pinconf_init_dev()
369 return -EINVAL; in ti_iodelay_pinconf_init_dev()
371 dev_dbg(iod->dev, "fine: ref=0x%04x delay=0x%04x fdpe=0x%08x\n", in ti_iodelay_pinconf_init_dev()
372 ival->fine_ref_count, ival->fine_delay_count, ival->fdpe); in ti_iodelay_pinconf_init_dev()
378 * ti_iodelay_get_pingroup() - Find the group mapped by a group selector
380 * @selector: Group Selector
382 * Return: Corresponding group representing group selector
389 g = pinctrl_generic_get_group(iod->pctl, selector); in ti_iodelay_get_pingroup()
391 dev_err(iod->dev, "%s could not find pingroup %i\n", __func__, in ti_iodelay_get_pingroup()
397 return g->data; in ti_iodelay_get_pingroup()
401 * ti_iodelay_offset_to_pin() - get a pin index based on the register offset
408 const struct ti_iodelay_reg_data *r = iod->reg_data; in ti_iodelay_offset_to_pin()
409 unsigned int index; in ti_iodelay_offset_to_pin() local
411 if (offset > r->regmap_config->max_register) { in ti_iodelay_offset_to_pin()
412 dev_err(iod->dev, "mux offset out of range: 0x%x (0x%x)\n", in ti_iodelay_offset_to_pin()
413 offset, r->regmap_config->max_register); in ti_iodelay_offset_to_pin()
414 return -EINVAL; in ti_iodelay_offset_to_pin()
417 index = (offset - r->reg_start_offset) / r->regmap_config->reg_stride; in ti_iodelay_offset_to_pin()
418 index /= r->reg_nr_per_pin; in ti_iodelay_offset_to_pin()
420 return index; in ti_iodelay_offset_to_pin()
424 * ti_iodelay_node_iterator() - Iterate iodelay node
428 * @pins: Array of pins in the pin group
429 * @pin_index: Pin index in the pin array
446 return -EINVAL; in ti_iodelay_node_iterator()
448 r = iod->reg_data; in ti_iodelay_node_iterator()
450 if (pinctrl_spec->args_count < r->reg_nr_per_pin) { in ti_iodelay_node_iterator()
451 dev_err(iod->dev, "invalid args_count for spec: %i\n", in ti_iodelay_node_iterator()
452 pinctrl_spec->args_count); in ti_iodelay_node_iterator()
454 return -EINVAL; in ti_iodelay_node_iterator()
457 /* Index plus two value cells */ in ti_iodelay_node_iterator()
458 cfg[pin_index].offset = pinctrl_spec->args[0]; in ti_iodelay_node_iterator()
459 cfg[pin_index].a_delay = pinctrl_spec->args[1] & 0xffff; in ti_iodelay_node_iterator()
460 cfg[pin_index].g_delay = pinctrl_spec->args[2] & 0xffff; in ti_iodelay_node_iterator()
464 dev_err(iod->dev, "could not add functions for %pOFn %ux\n", in ti_iodelay_node_iterator()
466 return -ENODEV; in ti_iodelay_node_iterator()
470 pd = &iod->pa[pin]; in ti_iodelay_node_iterator()
471 pd->drv_data = &cfg[pin_index]; in ti_iodelay_node_iterator()
473 dev_dbg(iod->dev, "%pOFn offset=%x a_delay = %d g_delay = %d\n", in ti_iodelay_node_iterator()
481 * ti_iodelay_dt_node_to_map() - Map a device tree node to appropriate group
487 * Maps the device tree description into a group of configuration parameters
500 const char *name = "pinctrl-pin-array"; in ti_iodelay_dt_node_to_map()
501 int rows, *pins, error = -EINVAL, i; in ti_iodelay_dt_node_to_map()
505 return -EINVAL; in ti_iodelay_dt_node_to_map()
511 *map = devm_kzalloc(iod->dev, sizeof(**map), GFP_KERNEL); in ti_iodelay_dt_node_to_map()
513 return -ENOMEM; in ti_iodelay_dt_node_to_map()
516 g = devm_kzalloc(iod->dev, sizeof(*g), GFP_KERNEL); in ti_iodelay_dt_node_to_map()
518 error = -ENOMEM; in ti_iodelay_dt_node_to_map()
522 pins = devm_kcalloc(iod->dev, rows, sizeof(*pins), GFP_KERNEL); in ti_iodelay_dt_node_to_map()
524 error = -ENOMEM; in ti_iodelay_dt_node_to_map()
528 cfg = devm_kcalloc(iod->dev, rows, sizeof(*cfg), GFP_KERNEL); in ti_iodelay_dt_node_to_map()
530 error = -ENOMEM; in ti_iodelay_dt_node_to_map()
548 g->cfg = cfg; in ti_iodelay_dt_node_to_map()
549 g->ncfg = i; in ti_iodelay_dt_node_to_map()
550 g->config = PIN_CONFIG_END; in ti_iodelay_dt_node_to_map()
552 error = pinctrl_generic_add_group(iod->pctl, np->name, pins, i, g); in ti_iodelay_dt_node_to_map()
556 (*map)->type = PIN_MAP_TYPE_CONFIGS_GROUP; in ti_iodelay_dt_node_to_map()
557 (*map)->data.configs.group_or_pin = np->name; in ti_iodelay_dt_node_to_map()
558 (*map)->data.configs.configs = &g->config; in ti_iodelay_dt_node_to_map()
559 (*map)->data.configs.num_configs = 1; in ti_iodelay_dt_node_to_map()
565 devm_kfree(iod->dev, cfg); in ti_iodelay_dt_node_to_map()
567 devm_kfree(iod->dev, pins); in ti_iodelay_dt_node_to_map()
569 devm_kfree(iod->dev, g); in ti_iodelay_dt_node_to_map()
571 devm_kfree(iod->dev, *map); in ti_iodelay_dt_node_to_map()
577 * ti_iodelay_pinconf_group_get() - Get the group configuration
579 * @selector: Group selector
582 * Return: The configuration if the group is valid, else returns -EINVAL
589 struct ti_iodelay_pingroup *group; in ti_iodelay_pinconf_group_get() local
592 group = ti_iodelay_get_pingroup(iod, selector); in ti_iodelay_pinconf_group_get()
594 if (!group) in ti_iodelay_pinconf_group_get()
595 return -EINVAL; in ti_iodelay_pinconf_group_get()
597 *config = group->config; in ti_iodelay_pinconf_group_get()
602 * ti_iodelay_pinconf_group_set() - Configure the groups of pins
604 * @selector: Group selector
617 struct ti_iodelay_pingroup *group; in ti_iodelay_pinconf_group_set() local
621 dev = iod->dev; in ti_iodelay_pinconf_group_set()
622 group = ti_iodelay_get_pingroup(iod, selector); in ti_iodelay_pinconf_group_set()
627 return -EINVAL; in ti_iodelay_pinconf_group_set()
632 return -EINVAL; in ti_iodelay_pinconf_group_set()
635 for (i = 0; i < group->ncfg; i++) { in ti_iodelay_pinconf_group_set()
636 if (ti_iodelay_pinconf_set(iod, &group->cfg[i])) in ti_iodelay_pinconf_group_set()
637 return -ENOTSUPP; in ti_iodelay_pinconf_group_set()
645 * ti_iodelay_pin_to_offset() - get pin register offset based on the pin index
647 * @selector: Pin index
652 const struct ti_iodelay_reg_data *r = iod->reg_data; in ti_iodelay_pin_to_offset()
655 offset = selector * r->regmap_config->reg_stride; in ti_iodelay_pin_to_offset()
656 offset *= r->reg_nr_per_pin; in ti_iodelay_pin_to_offset()
657 offset += r->reg_start_offset; in ti_iodelay_pin_to_offset()
674 r = iod->reg_data; in ti_iodelay_pin_dbg_show()
677 pd = &iod->pa[pin]; in ti_iodelay_pin_dbg_show()
678 cfg = pd->drv_data; in ti_iodelay_pin_dbg_show()
680 regmap_read(iod->regmap, offset, &in); in ti_iodelay_pin_dbg_show()
681 regmap_read(iod->regmap, offset + r->regmap_config->reg_stride, &oen); in ti_iodelay_pin_dbg_show()
682 regmap_read(iod->regmap, offset + r->regmap_config->reg_stride * 2, in ti_iodelay_pin_dbg_show()
686 iod->phys_base + offset, in ti_iodelay_pin_dbg_show()
687 cfg ? cfg->a_delay : -1, in ti_iodelay_pin_dbg_show()
688 cfg ? cfg->g_delay : -1, in ti_iodelay_pin_dbg_show()
693 * ti_iodelay_pinconf_group_dbg_show() - show the group information
694 * @pctldev: Show the group information
696 * @selector: Group selector
698 * Provide the configuration information of the selected group
705 struct ti_iodelay_pingroup *group; in ti_iodelay_pinconf_group_dbg_show() local
709 group = ti_iodelay_get_pingroup(iod, selector); in ti_iodelay_pinconf_group_dbg_show()
710 if (!group) in ti_iodelay_pinconf_group_dbg_show()
713 for (i = 0; i < group->ncfg; i++) { in ti_iodelay_pinconf_group_dbg_show()
717 cfg = &group->cfg[i]; in ti_iodelay_pinconf_group_dbg_show()
718 regmap_read(iod->regmap, cfg->offset, ®); in ti_iodelay_pinconf_group_dbg_show()
720 cfg->offset, reg, cfg->a_delay, cfg->g_delay); in ti_iodelay_pinconf_group_dbg_show()
744 * ti_iodelay_alloc_pins() - Allocate structures needed for pins for iodelay
754 const struct ti_iodelay_reg_data *r = iod->reg_data; in ti_iodelay_alloc_pins()
759 nr_pins = ti_iodelay_offset_to_pin(iod, r->regmap_config->max_register); in ti_iodelay_alloc_pins()
762 iod->pa = devm_kcalloc(dev, nr_pins, sizeof(*iod->pa), GFP_KERNEL); in ti_iodelay_alloc_pins()
763 if (!iod->pa) in ti_iodelay_alloc_pins()
764 return -ENOMEM; in ti_iodelay_alloc_pins()
766 iod->desc.pins = iod->pa; in ti_iodelay_alloc_pins()
767 iod->desc.npins = nr_pins; in ti_iodelay_alloc_pins()
769 phy_reg = r->reg_start_offset + base_phy; in ti_iodelay_alloc_pins()
772 pin = &iod->pa[i]; in ti_iodelay_alloc_pins()
773 pin->number = i; in ti_iodelay_alloc_pins()
817 {.compatible = "ti,dra7-iodelay", .data = &dra7_iodelay_data},
823 * ti_iodelay_probe() - Standard probe
830 struct device *dev = &pdev->dev; in ti_iodelay_probe()
831 struct device_node *np __free(device_node) = of_node_get(dev->of_node); in ti_iodelay_probe()
838 return -EINVAL; in ti_iodelay_probe()
843 return -ENOMEM; in ti_iodelay_probe()
845 iod->dev = dev; in ti_iodelay_probe()
846 iod->reg_data = device_get_match_data(dev); in ti_iodelay_probe()
847 if (!iod->reg_data) { in ti_iodelay_probe()
849 return -EINVAL; in ti_iodelay_probe()
853 iod->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in ti_iodelay_probe()
854 if (IS_ERR(iod->reg_base)) in ti_iodelay_probe()
855 return PTR_ERR(iod->reg_base); in ti_iodelay_probe()
857 iod->phys_base = res->start; in ti_iodelay_probe()
859 iod->regmap = devm_regmap_init_mmio(dev, iod->reg_base, in ti_iodelay_probe()
860 iod->reg_data->regmap_config); in ti_iodelay_probe()
861 if (IS_ERR(iod->regmap)) { in ti_iodelay_probe()
863 return PTR_ERR(iod->regmap); in ti_iodelay_probe()
870 ret = ti_iodelay_alloc_pins(dev, iod, res->start); in ti_iodelay_probe()
874 iod->desc.pctlops = &ti_iodelay_pinctrl_ops; in ti_iodelay_probe()
875 /* no pinmux ops - we are pinconf */ in ti_iodelay_probe()
876 iod->desc.confops = &ti_iodelay_pinctrl_pinconf_ops; in ti_iodelay_probe()
877 iod->desc.name = dev_name(dev); in ti_iodelay_probe()
878 iod->desc.owner = THIS_MODULE; in ti_iodelay_probe()
880 ret = devm_pinctrl_register_and_init(dev, &iod->desc, iod, &iod->pctl); in ti_iodelay_probe()
886 return pinctrl_enable(iod->pctl); in ti_iodelay_probe()