Lines Matching +full:group +full:- +full:index +full:- +full:bits

1 /* SPDX-License-Identifier: GPL-2.0-only */
38  * struct msm_pingroup - Qualcomm pingroup definition
39  * @grp:                  Generic data of the pin group (name and pins)
41  *                        this group. The index of the selected function is used
45  * @ctl_reg:              Offset of the register holding control bits for this group.
46  * @io_reg:               Offset of the register holding input/output bits for this group.
47  * @intr_cfg_reg:         Offset of the register holding interrupt configuration bits.
48  * @intr_status_reg:      Offset of the register holding the status bits for this group.
50  *                        from this group.
58  * @intr_enable_bit:      Offset in @intr_cfg_reg for enabling the interrupt for this group.
65  * @intr_target_width:    Number of bits used for specifying interrupt routing target.
71  * @intr_detection_width: Number of bits used for specifying interrupt type,
118  * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins
120  * @wakeirq:       The interrupt at the always-on interrupt controller
128  * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
143  * @egpio_func: If non-zero then this SoC supports eGPIO. Even though in
144  *              hardware this is a mux 1-level above the TLMM, we'll treat