| /linux-6.12.1/drivers/clk/ |
| D | clk-fixed-rate_test.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for clk fixed rate basic type
6 #include <linux/clk-provider.h>
17 #include "clk-fixed-rate_test.h"
20 * struct clk_hw_fixed_rate_kunit_params - Parameters to pass to __clk_hw_register_fixed_rate()
30 * @clk_fixed_flags: fixed rate specific clk flags
51 hw = __clk_hw_register_fixed_rate(params->dev, params->np, in clk_hw_register_fixed_rate_kunit_init()
52 params->name, in clk_hw_register_fixed_rate_kunit_init()
53 params->parent_name, in clk_hw_register_fixed_rate_kunit_init()
54 params->parent_hw, in clk_hw_register_fixed_rate_kunit_init()
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| D | clk-fixed-rate.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * Fixed rate clock implementation
9 #include <linux/clk-provider.h>
18 * DOC: basic fixed-rate clock that cannot gate
21 * prepare - clk_(un)prepare only ensures parents are prepared
22 * enable - clk_enable only ensures parents are enabled
23 * rate - rate is always a fixed value. No clk_set_rate support
24 * parent - fixed parent. No clk_set_parent support
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| D | clk-ep93xx.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Based on a rewrite of arch/arm/mach-ep93xx/clock.c:
13 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/cirrus,ep9301-syscon.h>
94 struct clk_hw *fixed[EP93XX_FIXED_CLK_COUNT]; member
105 return container_of(clk, struct ep93xx_clk_priv, reg[clk->idx]); in ep93xx_priv_from()
110 struct ep93xx_regmap_adev *aux = priv->aux_dev; in ep93xx_clk_write()
112 aux->write(aux->map, aux->lock, reg, val); in ep93xx_clk_write()
121 regmap_read(priv->map, clk->reg, &val); in ep93xx_clk_is_enabled()
123 return !!(val & BIT(clk->bit_idx)); in ep93xx_clk_is_enabled()
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| D | clk-fixed-factor.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
13 * DOC: basic fixed multiplier and divider clock that cannot gate
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
26 unsigned long long int rate; in clk_factor_recalc_rate() local
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
98 multi-function device has one fixed-rate oscillator, clocked
129 be pre-programmed to support other configurations and features not yet
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
196 For example, the CDCE925 contains two PLLs with spread-spectrum
198 the following setup, and uses a fixed setting for the output muxes.
206 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
218 This driver provides the fixed clocks and gates present on Airoha
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| D | clk-loongson1.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Clock driver for Loongson-1 SoC
5 * Copyright (C) 2012-2023 Keguang Zhang <keguang.zhang@gmail.com>
9 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/loongson,ls1x-clk.h>
26 u32 fixed; member
64 const struct ls1x_clk_pll_data *d = ls1x_clk->data; in ls1x_pll_recalc_rate()
65 u32 val, rate; in ls1x_pll_recalc_rate() local
67 val = readl(ls1x_clk->reg); in ls1x_pll_recalc_rate()
68 rate = d->fixed; in ls1x_pll_recalc_rate()
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| /linux-6.12.1/drivers/clk/sunxi/ |
| D | clk-a10-hosc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk-provider.h>
20 struct clk_fixed_rate *fixed; in sun4i_osc_clk_setup() local
22 const char *clk_name = node->name; in sun4i_osc_clk_setup()
23 u32 rate; in sun4i_osc_clk_setup() local
25 if (of_property_read_u32(node, "clock-frequency", &rate)) in sun4i_osc_clk_setup()
28 /* allocate fixed-rate and gate clock structs */ in sun4i_osc_clk_setup()
29 fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL); in sun4i_osc_clk_setup()
30 if (!fixed) in sun4i_osc_clk_setup()
36 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_osc_clk_setup()
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| D | clk-sunxi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
28 * PLL1 rate is calculated as follows
29 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
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| /linux-6.12.1/drivers/clk/tegra/ |
| D | clk-periph-fixed.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
19 struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw); in tegra_clk_periph_fixed_is_enabled() local
20 u32 mask = 1 << (fixed->num % 32), value; in tegra_clk_periph_fixed_is_enabled()
22 value = readl(fixed->base + fixed->regs->enb_reg); in tegra_clk_periph_fixed_is_enabled()
24 value = readl(fixed->base + fixed->regs->rst_reg); in tegra_clk_periph_fixed_is_enabled()
34 struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw); in tegra_clk_periph_fixed_enable() local
35 u32 mask = 1 << (fixed->num % 32); in tegra_clk_periph_fixed_enable()
37 writel(mask, fixed->base + fixed->regs->enb_set_reg); in tegra_clk_periph_fixed_enable()
44 struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw); in tegra_clk_periph_fixed_disable() local
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| /linux-6.12.1/drivers/clk/renesas/ |
| D | rcar-gen2-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen2 Clock Pulse Generator
10 #include <linux/clk-provider.h>
18 #include "renesas-cpg-mssr.h"
19 #include "rcar-gen2-cpg.h"
39 * prepare - clk_prepare only ensures that parents are prepared
40 * enable - clk_enable only ensures that parents are enabled
41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
42 * parent - fixed parent. No clk_set_parent support
60 val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT; in cpg_z_clk_recalc_rate()
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| D | rcar-gen3-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; in cpg_pll_clk_recalc_rate()
62 return parent_rate * mult * pll_clk->fixed_mult; in cpg_pll_clk_recalc_rate()
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| /linux-6.12.1/drivers/clk/qcom/ |
| D | common.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
10 #include <linux/clk-provider.h>
11 #include <linux/interconnect-clk.h>
12 #include <linux/reset-controller.h>
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
28 struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate) in qcom_find_freq() argument
33 if (!f->freq) in qcom_find_freq()
36 for (; f->freq; f++) in qcom_find_freq()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/modules/freesync/ |
| D | freesync.c | 2 * Copyright 2016-2023 Advanced Micro Devices, Inc.
34 /* Refresh rate ramp at a fixed rate of 65 Hz/second */
38 /* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
42 /* Threshold to exit fixed refresh rate */
44 /* Number of consecutive frames to check before entering/exiting fixed refresh */
71 core_freesync->dc = dc; in mod_freesync_create()
72 return &core_freesync->public; in mod_freesync_create()
118 * 10000) * stream->timing.h_total, in calc_duration_in_us_from_v_total()
119 stream->timing.pix_clk_100hz)); in calc_duration_in_us_from_v_total()
136 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), in mod_freesync_calc_v_total_from_refresh()
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| /linux-6.12.1/arch/mips/bcm63xx/ |
| D | clk.c | 23 unsigned int rate; member
33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
92 if (clk->id == 0) in enetx_set()
355 .rate = (50 * 1000 * 1000),
403 return clk->rate; in clk_get_rate()
408 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
414 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
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| /linux-6.12.1/drivers/clk/actions/ |
| D | owl-pll.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 // Author: David Liu <liuwei@actions-semi.com>
11 #include <linux/clk-provider.h>
16 #include "owl-pll.h"
18 static u32 owl_pll_calculate_mul(struct owl_pll_hw *pll_hw, unsigned long rate) in owl_pll_calculate_mul() argument
22 mul = DIV_ROUND_CLOSEST(rate, pll_hw->bfreq); in owl_pll_calculate_mul()
23 if (mul < pll_hw->min_mul) in owl_pll_calculate_mul()
24 mul = pll_hw->min_mul; in owl_pll_calculate_mul()
25 else if (mul > pll_hw->max_mul) in owl_pll_calculate_mul()
26 mul = pll_hw->max_mul; in owl_pll_calculate_mul()
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| /linux-6.12.1/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp-sck-kv-g-revB.dtso | 1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 /dts-v1/;
20 compatible = "xlnx,zynqmp-sk-kv260-rev2",
21 "xlnx,zynqmp-sk-kv260-rev1",
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| D | zynqmp-sck-kv-g-revA.dtso | 1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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| D | zynqmp-zc1751-xm015-dc1.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
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| /linux-6.12.1/Documentation/netlink/specs/ |
| D | tc.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
4 protocol: netlink-raw
12 -
16 -
19 -
23 -
26 -
29 -
32 -
35 -
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | fixed-mmio-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple memory mapped IO fixed-rate clock sources
10 This binding describes a fixed-rate clock for which the frequency can
11 be read from a single 32-bit memory mapped I/O register.
17 - Jan Kotas <jank@cadence.com>
21 const: fixed-mmio-clock
26 "#clock-cells":
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ti/ |
| D | fixed-factor-clock.txt | 1 Binding for TI fixed factor rate clock sources.
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : shall be "ti,fixed-factor-clock".
11 - #clock-cells : from common clock binding; shall be set to 0.
12 - ti,clock-div: fixed divider.
13 - ti,clock-mult: fixed multiplier.
14 - clocks: parent clock.
17 - clock-output-names : from common clock binding.
18 - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
20 - reg: offset for the autoidle register of this clock, see [2]
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| /linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_core_perf.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
16 * struct dpu_core_perf_params - definition of performance parameters
19 * @core_clk_rate: core clock rate request
28 * struct dpu_core_perf_tune - definition of performance tuning control
36 * struct dpu_core_perf - definition of core performance context
37 * @perf_cfg: Platform-specific performance configuration
38 * @core_clk_rate: current core clock rate
39 * @max_core_clk_rate: maximum allowable core clock rate
42 * @fix_core_clk_rate: fixed core clock request in Hz used in mode 2
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| /linux-6.12.1/drivers/clk/davinci/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
12 #include <linux/clk-provider.h>
22 #include <linux/platform_data/clk-davinci-pll.h>
79 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
86 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
90 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
96 * struct davinci_pll_clk - Main PLL clock (aka PLLOUT)
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| /linux-6.12.1/drivers/clk/samsung/ |
| D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
14 #include "clk-pll.h"
15 #include "clk-cpu.h"
18 * struct samsung_clk_provider - information about clock provider
21 * @lock: maintains exclusion between callbacks for a given clock-provider
33 * struct samsung_clock_alias - information about mux clock
54 * struct samsung_fixed_rate_clock - information about fixed-rate clock
56 * @name: name of this fixed-rate clock
58 * @flags: optional fixed-rate clock flags
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| /linux-6.12.1/include/linux/ |
| D | clk-provider.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
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