Lines Matching +full:fixed +full:- +full:rate

1 # SPDX-License-Identifier: GPL-2.0
59 	  Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
88 	  These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
98 	  multi-function device has one fixed-rate oscillator, clocked
129 	  be pre-programmed to support other configurations and features not yet
178 	  This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
196 	  For example, the CDCE925 contains two PLLs with spread-spectrum
198 	  the following setup, and uses a fixed setting for the output muxes.
206 	tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
218 	  This driver provides the fixed clocks and gates present on Airoha
285 	  clock. These multi-function devices have two (S2MPS14) or three
286 	  (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
310 	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
336 	  Support for the APM X-Gene SoC reference, PLL, and device clocks.
346 	bool "Clock driver for Loongson-2 SoC"
349           This driver provides support for clock controller on Loongson-2 SoC.
352           Say Y here to support Loongson-2 SoC clock driver.
381 	tristate "Clock driver for Renesas 9-series PCIe clock generators"
386 	  This driver supports the Renesas 9-series PCIe clock generator
454 	bool "Clock driver for Memory Mapped Fixed values"
458 	  Support for Memory Mapped IO Fixed clocks
465 	  Support for the Canaan Kendryte K210 RISC-V SoC clocks.
479 source "drivers/clk/baikal-t1/Kconfig"
504 source "drivers/clk/sunxi-ng/Kconfig"
526 	tristate "Basic fixed rate clk type KUnit test" if !KUNIT_ALL_TESTS
532 	  KUnit tests for the basic fixed rate clk type.
547 	  Kunit test for the clk-fractional-divider type.