Lines Matching +full:fixed +full:- +full:rate
1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; in cpg_pll_clk_recalc_rate()
62 return parent_rate * mult * pll_clk->fixed_mult; in cpg_pll_clk_recalc_rate()
72 prate = req->best_parent_rate * pll_clk->fixed_mult; in cpg_pll_clk_determine_rate()
73 min_mult = max(div64_ul(req->min_rate, prate), 1ULL); in cpg_pll_clk_determine_rate()
74 max_mult = min(div64_ul(req->max_rate, prate), 128ULL); in cpg_pll_clk_determine_rate()
76 return -EINVAL; in cpg_pll_clk_determine_rate()
78 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); in cpg_pll_clk_determine_rate()
81 req->rate = prate * mult; in cpg_pll_clk_determine_rate()
85 static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, in cpg_pll_clk_set_rate() argument
92 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult); in cpg_pll_clk_set_rate()
95 val = readl(pll_clk->pllcr_reg); in cpg_pll_clk_set_rate()
97 val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK); in cpg_pll_clk_set_rate()
98 writel(val, pll_clk->pllcr_reg); in cpg_pll_clk_set_rate()
100 for (i = 1000; i; i--) { in cpg_pll_clk_set_rate()
101 if (readl(pll_clk->pllecr_reg) & pll_clk->pllecr_pllst_mask) in cpg_pll_clk_set_rate()
107 return -ETIMEDOUT; in cpg_pll_clk_set_rate()
130 return ERR_PTR(-ENOMEM); in cpg_pll_clk_register()
137 pll_clk->hw.init = &init; in cpg_pll_clk_register()
138 pll_clk->pllcr_reg = base + offset; in cpg_pll_clk_register()
139 pll_clk->pllecr_reg = base + CPG_PLLECR; in cpg_pll_clk_register()
140 pll_clk->fixed_mult = mult; /* PLL refclk x (setting + 1) x mult */ in cpg_pll_clk_register()
141 pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index); in cpg_pll_clk_register()
143 clk = clk_register(NULL, &pll_clk->hw); in cpg_pll_clk_register()
154 * prepare - clk_prepare only ensures that parents are prepared
155 * enable - clk_enable only ensures that parents are enabled
156 * rate - rate is adjustable.
157 * clk->rate = (parent->rate * mult / 32 ) / fixed_div
158 * parent - fixed parent. No clk_set_parent support
168 unsigned long max_rate; /* Maximum rate for normal mode */
182 val = readl(zclk->reg) & zclk->mask; in cpg_z_clk_recalc_rate()
183 mult = 32 - (val >> __ffs(zclk->mask)); in cpg_z_clk_recalc_rate()
186 32 * zclk->fixed_div); in cpg_z_clk_recalc_rate()
194 unsigned long rate, prate; in cpg_z_clk_determine_rate() local
196 rate = min(req->rate, req->max_rate); in cpg_z_clk_determine_rate()
197 if (rate <= zclk->max_rate) { in cpg_z_clk_determine_rate()
198 /* Set parent rate to initial value for normal modes */ in cpg_z_clk_determine_rate()
199 prate = zclk->max_rate; in cpg_z_clk_determine_rate()
201 /* Set increased parent rate for boost modes */ in cpg_z_clk_determine_rate()
202 prate = rate; in cpg_z_clk_determine_rate()
204 req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), in cpg_z_clk_determine_rate()
205 prate * zclk->fixed_div); in cpg_z_clk_determine_rate()
207 prate = req->best_parent_rate / zclk->fixed_div; in cpg_z_clk_determine_rate()
208 min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL); in cpg_z_clk_determine_rate()
209 max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL); in cpg_z_clk_determine_rate()
211 return -EINVAL; in cpg_z_clk_determine_rate()
213 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate); in cpg_z_clk_determine_rate()
216 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32); in cpg_z_clk_determine_rate()
220 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, in cpg_z_clk_set_rate() argument
227 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, in cpg_z_clk_set_rate()
231 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) in cpg_z_clk_set_rate()
232 return -EBUSY; in cpg_z_clk_set_rate()
234 cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); in cpg_z_clk_set_rate()
240 cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK); in cpg_z_clk_set_rate()
246 * ~10 iterations are needed, independently of the CPU rate. in cpg_z_clk_set_rate()
247 * Since this value might be dependent on external xtal rate, pll1 in cpg_z_clk_set_rate()
248 * rate or even the other emulation clocks rate, use 1000 as a in cpg_z_clk_set_rate()
251 for (i = 1000; i; i--) { in cpg_z_clk_set_rate()
252 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) in cpg_z_clk_set_rate()
258 return -ETIMEDOUT; in cpg_z_clk_set_rate()
281 return ERR_PTR(-ENOMEM); in __cpg_z_clk_register()
289 zclk->reg = reg + fcr; in __cpg_z_clk_register()
290 zclk->kick_reg = reg + CPG_FRQCRB; in __cpg_z_clk_register()
291 zclk->hw.init = &init; in __cpg_z_clk_register()
292 zclk->mask = GENMASK(offset + 4, offset); in __cpg_z_clk_register()
293 zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ in __cpg_z_clk_register()
295 clk = clk_register(NULL, &zclk->hw); in __cpg_z_clk_register()
301 zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) / in __cpg_z_clk_register()
302 zclk->fixed_div; in __cpg_z_clk_register()
357 parent = clks[core->parent & 0xffff]; /* some types use high bits */ in rcar_gen3_cpg_clk_register()
361 switch (core->type) { in rcar_gen3_cpg_clk_register()
363 div = cpg_pll_config->extal_div; in rcar_gen3_cpg_clk_register()
372 return cpg_pll_clk_register(core->name, __clk_get_name(parent), in rcar_gen3_cpg_clk_register()
376 mult = cpg_pll_config->pll1_mult; in rcar_gen3_cpg_clk_register()
377 div = cpg_pll_config->pll1_div; in rcar_gen3_cpg_clk_register()
386 return cpg_pll_clk_register(core->name, __clk_get_name(parent), in rcar_gen3_cpg_clk_register()
390 mult = cpg_pll_config->pll3_mult; in rcar_gen3_cpg_clk_register()
391 div = cpg_pll_config->pll3_div; in rcar_gen3_cpg_clk_register()
397 * fixed factor clock for now as there's no generic multiplier in rcar_gen3_cpg_clk_register()
406 return cpg_sdh_clk_register(core->name, base + core->offset, in rcar_gen3_cpg_clk_register()
410 return cpg_sd_clk_register(core->name, base + core->offset, in rcar_gen3_cpg_clk_register()
419 return ERR_PTR(-ENOMEM); in rcar_gen3_cpg_clk_register()
421 csn->reg = base + CPG_RCKCR; in rcar_gen3_cpg_clk_register()
427 value = readl(csn->reg) & 0x3f; in rcar_gen3_cpg_clk_register()
434 writel(value, csn->reg); in rcar_gen3_cpg_clk_register()
446 * Clock selectable between two parents and two fixed dividers in rcar_gen3_cpg_clk_register()
449 if (cpg_mode & BIT(core->offset)) { in rcar_gen3_cpg_clk_register()
450 div = core->div & 0xffff; in rcar_gen3_cpg_clk_register()
452 parent = clks[core->parent >> 16]; in rcar_gen3_cpg_clk_register()
455 div = core->div >> 16; in rcar_gen3_cpg_clk_register()
461 return cpg_z_clk_register(core->name, __clk_get_name(parent), in rcar_gen3_cpg_clk_register()
462 base, core->div, core->offset); in rcar_gen3_cpg_clk_register()
465 return cpg_zg_clk_register(core->name, __clk_get_name(parent), in rcar_gen3_cpg_clk_register()
466 base, core->div, core->offset); in rcar_gen3_cpg_clk_register()
470 * Clock combining OSC EXTAL predivider and a fixed divider in rcar_gen3_cpg_clk_register()
472 div = cpg_pll_config->osc_prediv * core->div; in rcar_gen3_cpg_clk_register()
477 * Clock selectable between two parents and two fixed dividers in rcar_gen3_cpg_clk_register()
481 div = core->div & 0xffff; in rcar_gen3_cpg_clk_register()
483 parent = clks[core->parent >> 16]; in rcar_gen3_cpg_clk_register()
486 div = core->div >> 16; in rcar_gen3_cpg_clk_register()
491 return clk_register_divider_table(NULL, core->name, in rcar_gen3_cpg_clk_register()
499 * Register RPCSRC as fixed factor clock based on the in rcar_gen3_cpg_clk_register()
513 parent = clks[core->parent >> 16]; in rcar_gen3_cpg_clk_register()
516 div = core->div; in rcar_gen3_cpg_clk_register()
526 return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR, in rcar_gen3_cpg_clk_register()
530 return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR, in rcar_gen3_cpg_clk_register()
534 return ERR_PTR(-EINVAL); in rcar_gen3_cpg_clk_register()
537 return clk_register_fixed_factor(NULL, core->name, in rcar_gen3_cpg_clk_register()
551 cpg_quirks = (uintptr_t)attr->data; in rcar_gen3_cpg_init()