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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Dapple,aic2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
21 - Software triggering (ORed with hw line)
22 - Automatic prioritization (single event/ack register per CPU, lower IRQs =
[all …]
Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
22 - Automatic masking on event delivery (auto-ack)
23 - Software triggering (ORed with hw line)
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/linux-6.12.1/fs/fuse/
Ddev.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
42 * Lockless access is OK, because file->private data is set in fuse_get_dev()
45 return READ_ONCE(file->private_data); in fuse_get_dev()
50 INIT_LIST_HEAD(&req->list); in fuse_request_init()
51 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
52 init_waitqueue_head(&req->waitq); in fuse_request_init()
53 refcount_set(&req->count, 1); in fuse_request_init()
54 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
55 req->fm = fm; in fuse_request_init()
74 refcount_inc(&req->count); in __fuse_get_request()
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Dvirtio_fs.c1 // SPDX-License-Identifier: GPL-2.0
3 * virtio-fs: Virtio Filesystem
31 /* List of virtio-fs device instances and a lock for the list. Also provides
47 /* Per-virtqueue state */
50 struct virtqueue *vq; /* protected by ->lock */
63 /* A virtio-fs device instance */
74 unsigned int *mq_map; /* index = cpu id, value = request vq id */
124 struct fuse_fs_context *ctx = fsc->fs_private; in virtio_fs_parse_param()
133 ctx->dax_mode = FUSE_DAX_ALWAYS; in virtio_fs_parse_param()
136 ctx->dax_mode = result.uint_32; in virtio_fs_parse_param()
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Dfuse_i.h3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
23 #include <linux/backing-dev.h>
41 /** Bias for fi->writectr, meaning new writepages must not be sent */
110 /** The sticky bit in inode->i_mode may have been removed, so
126 /* Files usable in writepage. Protected by fi->lock */
142 /* waitq for direct-io completion */
257 /** RB node to be linked on fuse_conn->polled_files */
263 /** Does file hold a fi->iocachectr refcount? */
398 * - FR_ABORTED
399 * - FR_LOCKED (may also be modified under fc->lock, tested under both)
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/linux-6.12.1/arch/arm64/boot/dts/apple/
Dt6001.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
15 #include "multi-die-cpp.h"
17 #include "t600x-common.dtsi"
20 compatible = "apple,t6001", "apple,arm-platform";
23 compatible = "simple-bus";
24 #address-cells = <2>;
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Dt6002.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
15 #include "multi-die-cpp.h"
17 #include "t600x-common.dtsi"
20 compatible = "apple,t6002", "apple,arm-platform";
22 #address-cells = <2>;
23 #size-cells = <2>;
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Dt8103.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 compatible = "apple,t8103", "apple,arm-platform";
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <2>;
23 #size-cells = <0>;
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Dt8112.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
17 compatible = "apple,t8112", "apple,arm-platform";
19 #address-cells = <2>;
20 #size-cells = <2>;
23 #address-cells = <2>;
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/linux-6.12.1/drivers/irqchip/
Dirq-apple-aic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on irq-lpc32xx:
6 * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
7 * Based on irq-bcm2836:
14 * - 896 level-triggered hardware IRQs
15 * - Single mask bit per IRQ
16 * - Per-IRQ affinity setting
17 * - Automatic masking on event delivery (auto-ack)
18 * - Software triggering (ORed with hw line)
19 * - 2 per-CPU IPIs (meant as "self" and "other", but they are
[all …]
Dirq-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0+
29 * The FIQ control register:
30 * Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
31 * Bit 7: Enable FIQ generation
34 * An interrupt must be disabled before configuring it for FIQ generation
94 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]); in armctrl_mask_irq()
99 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]); in armctrl_unmask_irq()
103 .name = "ARMCTRL-level",
115 return -EINVAL; in armctrl_xlate()
118 return -EINVAL; in armctrl_xlate()
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Dirq-gic-v3.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
26 #include <linux/irqchip/arm-gic-common.h>
27 #include <linux/irqchip/arm-gic-v3.h>
28 #include <linux/irqchip/arm-gic-v3-prio.h>
29 #include <linux/irqchip/irq-partition-percpu.h>
32 #include <linux/arm-smccc.h>
39 #include "irq-gic-common.h"
95 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
99 * When security is enabled, non-secure priority values from the (re)distributor
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Dirq-armada-370-xp.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
45 * +---------------+ +---------------+
47 * | per-CPU | | per-CPU |
51 * +---------------+ +---------------+
56 * +-------------------+
61 * +-------------------+
69 * registers, which are relative to "mpic->base".
71 * The "per-CPU mask/unmask" is modified using the MPIC_INT_SET_MASK
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/linux-6.12.1/arch/arm/mach-imx/
Dtzic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
20 #include "irq-common.h"
54 unsigned int index, mask, value; in tzic_set_irq_fiq() local
56 index = hwirq >> 5; in tzic_set_irq_fiq()
57 if (unlikely(index >= 4)) in tzic_set_irq_fiq()
58 return -EINVAL; in tzic_set_irq_fiq()
61 value = imx_readl(tzic_base + TZIC_INTSEC0(index)) | mask; in tzic_set_irq_fiq()
64 imx_writel(value, tzic_base + TZIC_INTSEC0(index)); in tzic_set_irq_fiq()
76 int idx = d->hwirq >> 5; in tzic_irq_suspend()
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/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dfsl,ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
18 DMA controller to use, but the channels themselves are hard-wired. The
22 "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
23 "fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
24 "fsl,mpc8610-dma-channel") can remain. If these nodes are left as
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/linux-6.12.1/sound/soc/fsl/
Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
17 // manually skip this data in the FIQ handler. With sampling rates different
19 // between pcm data and GPIO status data changes. Our FIQ handler is not
43 #include <linux/dma/imx-dma.h>
53 #include "imx-pcm.h"
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
66 * (bit-endianness must match byte-endianness). Processors typically write
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/linux-6.12.1/drivers/clocksource/
Dtimer-tegra186.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2020 NVIDIA Corporation. All rights reserved.
63 unsigned int index; member
71 unsigned int index; member
95 writel_relaxed(value, tmr->regs + offset); in tmr_writel()
100 writel_relaxed(value, wdt->regs + offset); in wdt_writel()
105 return readl_relaxed(wdt->regs + offset); in wdt_readl()
109 unsigned int index) in tegra186_tmr_create() argument
111 unsigned int offset = 0x10000 + index * 0x10000; in tegra186_tmr_create()
114 tmr = devm_kzalloc(tegra->dev, sizeof(*tmr), GFP_KERNEL); in tegra186_tmr_create()
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/linux-6.12.1/arch/arm/probes/kprobes/
Dtest-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/probes/kprobes/test-core.h
41 * Store the given value into the stack buffer at [SP+index].
70 u8 index; member
107 verbose("---------------------------------------------------------\n");
134 #define TEST_ARG_MEM(index, val) \ argument
136 ".byte "#index" \n\t" \
149 ".short 50f-0f \n\t" \
150 ".short 2f-0f \n\t" \
151 ".short 99f-0f \n\t" \
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/linux-6.12.1/arch/arm64/kernel/
Dsetup.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1995-2001 Russell King
105 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
106 * level in order to build a linear index from an
115 * Pre-scan the list of MPIDRS and filter out bits that do in smp_build_mpidr_hash()
133 fs[i] = affinity ? ffs(affinity) - 1 : 0; in smp_build_mpidr_hash()
134 bits[i] = ls - fs[i]; in smp_build_mpidr_hash()
137 * An index can be created from the MPIDR_EL1 by isolating the in smp_build_mpidr_hash()
147 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0]; in smp_build_mpidr_hash()
148 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] - in smp_build_mpidr_hash()
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/linux-6.12.1/arch/arm64/kvm/vgic/
Dvgic-v3.c1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/irqchip/arm-gic-v3.h>
24 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; in vgic_v3_set_underflow()
26 cpuif->vgic_hcr |= ICH_HCR_UIE; in vgic_v3_set_underflow()
37 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; in vgic_v3_fold_lr_state()
38 struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3; in vgic_v3_fold_lr_state()
39 u32 model = vcpu->kvm->arch.vgic.vgic_model; in vgic_v3_fold_lr_state()
44 cpuif->vgic_hcr &= ~ICH_HCR_UIE; in vgic_v3_fold_lr_state()
46 for (lr = 0; lr < cpuif->used_lrs; lr++) { in vgic_v3_fold_lr_state()
47 u64 val = cpuif->vgic_lr[lr]; in vgic_v3_fold_lr_state()
[all …]
/linux-6.12.1/arch/arm/mach-rpc/
Decard.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 1995-2001 Russell King
11 * 08-Dec-1996 RMK Added code for the 9'th expansion card - the ether
13 * 06-May-1997 RMK Added blacklist for cards whose loader doesn't work.
14 * 12-Sep-1997 RMK Created new handling of interrupt enables/disables
15 * - cards can now register their own routine to control
17 * 29-Sep-1997 RMK Expansion card interrupt hardware not being re-enabled
20 * 15-Feb-1998 RMK Added DMA support
21 * 12-Sep-1998 RMK Added EASI support
22 * 10-Jan-1999 RMK Run loaders in a simulated RISC OS environment.
[all …]
/linux-6.12.1/arch/arm/kernel/
Dsetup.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1995-2001 Russell King
46 #include <asm/mach-types.h>
140 u32 fiq[4]; member
300 /* I-cache aliases will be handled by D-cache aliasing code */ in cpu_has_aliasing_icache()
353 * These functions re-use the assembly code in head.S, which
527 * cpu_init - initialise one CPU.
529 * cpu_init sets up the per-CPU stacks.
552 * In Thumb-2, msr with an immediate value is not allowed. in cpu_init()
563 * setup stacks for re-entrant exception handlers in cpu_init()
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/linux-6.12.1/drivers/remoteproc/
Dxlnx_r5_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/power/xlnx-zynqmp-power.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/firmware/xlnx-zynqmp.h>
12 #include <linux/mailbox/zynqmp-ipi-message.h>
34 * reflects possible values of xlnx,cluster-mode dt-property
38 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */
43 * struct mem_bank_data - Memory Bank description
48 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off
60 * struct zynqmp_sram_bank - sram bank description
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/linux-6.12.1/arch/arm/boot/compressed/
Dhead.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2002 Russell King
12 #include "efi-header.S"
20 AR_CLASS( .arch armv7-a )
21 M_CLASS( .arch armv7-m )
101 kputc #'-'
105 kputc #'-'
110 kputc #'-'
154 * in little-endian form.
234 * Booting from Angel - need to enter SVC mode and disable
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/linux-6.12.1/arch/arm64/kvm/
Darm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
9 #include <linux/entry-kvm.h>
85 * This functions as an allow-list of protected VM capabilities.
112 int r = -EINVAL; in kvm_vm_ioctl_enable_cap()
114 if (cap->flags) in kvm_vm_ioctl_enable_cap()
115 return -EINVAL; in kvm_vm_ioctl_enable_cap()
117 if (kvm_vm_is_protected(kvm) && !pkvm_ext_allowed(kvm, cap->cap)) in kvm_vm_ioctl_enable_cap()
118 return -EINVAL; in kvm_vm_ioctl_enable_cap()
120 switch (cap->cap) { in kvm_vm_ioctl_enable_cap()
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